Date: Tue, 23 Nov 1999 11:42:11 -0800 (PST) From: Matthew Dillon <dillon@apollo.backplane.com> To: Alfred Perlstein <bright@wintelcom.net> Cc: Alan Cox <alc@cs.rice.edu>, Poul-Henning Kamp <phk@critter.freebsd.dk>, Peter Wemm <peter@netplex.com.au>, Tommy Hallgren <thallgren@yahoo.com>, freebsd-smp@FreeBSD.ORG Subject: Re: Matt's new unlock optimiazation Message-ID: <199911231942.LAA11156@apollo.backplane.com> References: <Pine.BSF.4.21.9911231156020.4557-100000@fw.wintelcom.net>
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:I'm a bit confused by this, I take it to mean that there's really
:nothing wrong with the lock behavior however, if there are outstanding
:memory transactions to handle then they may actually be done after
:we've released the lock by the CPU that's released it.
:
:And that those memory operations rely on the mutual exclusion of
:the lock, so basically you have this sort of window:
:
: CPU a (has lock) CPU b (wants lock)
:
: mem write A
: mem read B
: mem write C
: RELEASE lock
There is only one sequence of events that I believe can cause a
problem, at least from my read of the app note:
mem read A
RELEASE lock (mem write X)
In this case the instruction that runs 'mem read A' may be executed
out of order from the instruction which writes X. Since location A
does not conflict with the address of the lock, Intel's current spec
allows the out of order execution to occur.
I'm not sure how intel's speculative read works. They seem to imply
that it goes into the cache, in which case cache coherency protocols
will prevent a conflict. But if it goes into the execution unit's
data buffer or if the instructions are actually executed out of order,
we have a problem.
Intel says that writes are ordered, so pending writes prior to
release will not be a problem (no need for a locked instruction).
We are left with mixed reads and writes.
No sense taking any chances, it only costs us 55nS (on a P3-450).
-Matt
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