Date: Sat, 18 Jan 2014 19:30:43 -0600 From: Nathan Whitehorn <nwhitehorn@freebsd.org> To: Julien Grall <julien.grall@linaro.org>, Warner Losh <imp@bsdimp.com> Cc: ian.campbell@citrix.com, stefano.stabellini@eu.citrix.com, xen-devel@lists.xen.org, freebsd-xen@freebsd.org, freebsd-arm@FreeBSD.org, gibbs@freebsd.org Subject: Re: [RFC] Add support for Xen ARM guest on FreeBSD Message-ID: <52DB2AC3.5000206@freebsd.org> In-Reply-To: <52DB1138.6010804@linaro.org> References: <1389733267-20822-1-git-send-email-julien.grall@linaro.org> <24851B79-7EC7-4E3A-94DB-4B9B86FDFFFC@bsdimp.com> <52D6B62A.9000208@linaro.org> <52D73C4E.2080306@freebsd.org> <52D87B15.5090208@linaro.org> <52D89DC9.7050303@freebsd.org> <52DB1138.6010804@linaro.org>
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On 01/18/14 17:41, Julien Grall wrote:
>
> Hello Nathan,
>
> On 01/17/2014 03:04 AM, Nathan Whitehorn wrote:
>> On 01/16/14 18:36, Julien Grall wrote:
>>>
>>>
>>> On 01/16/2014 01:56 AM, Nathan Whitehorn wrote:
>>> As I understand, only the simple bus code (see simplebus_attach) is
>>> translating the interrupts in the device on a resource.
>>> So if you have a node directly attached to the root node with
>>> interrupts and MMIO, the driver won't be able to retrieve and
>>> translate the interrupts via bus_alloc_resources.
>
>> Why not? nexus on ARM, MIPS, PowerPC, and sparc64 can do this.
>
> I have digged into the code to find the reason of my issue. FreeBSD is
> receiving a VM fault when the driver (xen-dt) is trying to setup the IRQ.
>
> This is because the GIC is not yet initialized but FreeBSD asks to
> unmask the IRQ (sys/arm/arm/gic.c:306).
>
> With this problem, all device nodes that are before the GIC in the
> device tree can't have interrupts. For instance this simple device
> will segfault on FreeBSD:
>
> / {
>
> mybus {
> compatible = "simple-bus";
>
> mynode {
> interrupt-parent = &gic;
> interrupts = <...>;
> };
>
> gic: gic@xxxx {
> interrupt-controller;
> }
> };
> };
>
> The node "mynode" will have to move after the GIC to be able to work
> correctly.
>
Ah, that sounds like a bug in the interrupt handling code. The PPC code
is designed to handle this problem by deferring interrupt setup, as well
as a number of other latent issues, and I think would make a good match
for ARM as well. I made an experimental branch to port it to MIPS (the
code is almost entirely machine-independent) but am waiting for testing.
A general solution to this problem has to involve deferred setup.
-Nathan
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