Date: Thu, 6 May 2010 18:43:01 +0000 (UTC) From: Pyun YongHyeon <yongari@FreeBSD.org> To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-stable@freebsd.org, svn-src-stable-8@freebsd.org Subject: svn commit: r207718 - stable/8/sys/dev/msk Message-ID: <201005061843.o46Ih1NB057902@svn.freebsd.org>
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Author: yongari Date: Thu May 6 18:43:00 2010 New Revision: 207718 URL: http://svn.freebsd.org/changeset/base/207718 Log: MFC r207409,207442: r207409: Both RX_GMF_LP_THR and RX_GMF_UP_THR must be 16 bits register. If it is 8bits register then RX FIFO size can't exceed 2KB which is not true for almost all Yukon II controller. r207442: Disable non-ASF packet flushing on Yukon Extreme as vendor's driver does. Without this change, Yukon Extreme seems to generate lots of RX FIFO overruns even though controller has available RX buffers. These excessive RX FIFO overruns generated lots of pause frames which in turn killed devices plugged into switch. It seems there is still occasional RX frame corruption on Yukon Extreme but this change seems to fix the pause frame storm. Reported by: jhb Tested by: jhb Modified: stable/8/sys/dev/msk/if_msk.c stable/8/sys/dev/msk/if_mskreg.h Directory Properties: stable/8/sys/ (props changed) stable/8/sys/amd64/include/xen/ (props changed) stable/8/sys/cddl/contrib/opensolaris/ (props changed) stable/8/sys/contrib/dev/acpica/ (props changed) stable/8/sys/contrib/pf/ (props changed) stable/8/sys/dev/xen/xenpci/ (props changed) stable/8/sys/geom/sched/ (props changed) Modified: stable/8/sys/dev/msk/if_msk.c ============================================================================== --- stable/8/sys/dev/msk/if_msk.c Thu May 6 18:38:19 2010 (r207717) +++ stable/8/sys/dev/msk/if_msk.c Thu May 6 18:43:00 2010 (r207718) @@ -3673,9 +3673,9 @@ msk_init_locked(struct msk_if_softc *sc_ if ((sc_if->msk_flags & MSK_FLAG_RAMBUF) == 0) { /* Set Rx Pause threshould. */ - CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, RX_GMF_LP_THR), + CSR_WRITE_2(sc, MR_ADDR(sc_if->msk_port, RX_GMF_LP_THR), MSK_ECU_LLPP); - CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, RX_GMF_UP_THR), + CSR_WRITE_2(sc, MR_ADDR(sc_if->msk_port, RX_GMF_UP_THR), MSK_ECU_ULPP); /* Configure store-and-forward for Tx. */ msk_set_tx_stfwd(sc_if); @@ -3763,6 +3763,11 @@ msk_init_locked(struct msk_if_softc *sc_ msk_stop(sc_if); return; } + if (sc->msk_hw_id == CHIP_ID_YUKON_EX) { + /* Disable flushing of non-ASF packets. */ + CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), + GMF_RX_MACSEC_FLUSH_OFF); + } /* Configure interrupt handling. */ if (sc_if->msk_port == MSK_PORT_A) { Modified: stable/8/sys/dev/msk/if_mskreg.h ============================================================================== --- stable/8/sys/dev/msk/if_mskreg.h Thu May 6 18:38:19 2010 (r207717) +++ stable/8/sys/dev/msk/if_mskreg.h Thu May 6 18:43:00 2010 (r207718) @@ -621,8 +621,8 @@ #define RX_GMF_FL_MSK 0x0c4c /* 32 bit Rx GMAC FIFO Flush Mask */ #define RX_GMF_FL_THR 0x0c50 /* 32 bit Rx GMAC FIFO Flush Threshold */ #define RX_GMF_TR_THR 0x0c54 /* 32 bit Rx Truncation Threshold (Yukon-2) */ -#define RX_GMF_UP_THR 0x0c58 /* 8 bit Rx Upper Pause Thr (Yukon-EC_U) */ -#define RX_GMF_LP_THR 0x0c5a /* 8 bit Rx Lower Pause Thr (Yukon-EC_U) */ +#define RX_GMF_UP_THR 0x0c58 /* 16 bit Rx Upper Pause Thr (Yukon-EC_U) */ +#define RX_GMF_LP_THR 0x0c5a /* 16 bit Rx Lower Pause Thr (Yukon-EC_U) */ #define RX_GMF_VLAN 0x0c5c /* 32 bit Rx VLAN Type Register (Yukon-2) */ #define RX_GMF_WP 0x0c60 /* 32 bit Rx GMAC FIFO Write Pointer */ #define RX_GMF_WLEV 0x0c68 /* 32 bit Rx GMAC FIFO Write Level */ @@ -1941,6 +1941,8 @@ #define RX_TRUNC_OFF BIT_26 /* disable packet truncation */ #define RX_VLAN_STRIP_ON BIT_25 /* enable VLAN stripping */ #define RX_VLAN_STRIP_OFF BIT_24 /* disable VLAN stripping */ +#define GMF_RX_MACSEC_FLUSH_ON BIT_23 +#define GMF_RX_MACSEC_FLUSH_OFF BIT_22 #define GMF_RX_OVER_ON BIT_19 /* enable flushing on receive overrun */ #define GMF_RX_OVER_OFF BIT_18 /* disable flushing on receive overrun */ #define GMF_ASF_RX_OVER_ON BIT_17 /* enable flushing of ASF when overrun */
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