From owner-freebsd-embedded@FreeBSD.ORG Mon Dec 5 01:33:21 2011 Return-Path: Delivered-To: freebsd-embedded@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id 1FB5F1065677 for ; Mon, 5 Dec 2011 01:33:21 +0000 (UTC) (envelope-from adrian.chadd@gmail.com) Received: from mail-vw0-f54.google.com (mail-vw0-f54.google.com [209.85.212.54]) by mx1.freebsd.org (Postfix) with ESMTP id C84298FC16 for ; Mon, 5 Dec 2011 01:33:20 +0000 (UTC) Received: by vbbfr13 with SMTP id fr13so5661214vbb.13 for ; Sun, 04 Dec 2011 17:33:20 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=mime-version:sender:in-reply-to:references:date :x-google-sender-auth:message-id:subject:from:to:cc:content-type :content-transfer-encoding; bh=k1lwgW0AfsuUZ0VZ4JVWlLcTWnGxgG6MZ4uTR45WBR0=; b=T5r9QS1vVTwQ6kPXxvk9fGDi/AsCx5DA49pMauGB/jzKVTwSHtMz8DudAsp5kpctT4 yxbQDHT5jWgz/VoGrhzAc6ucWuwlvORICPaQBXZ58TqB1diQ7fwmm6sandjOcjvNKvJQ YyTYUcooYdF1k/W4NAlGt5vmQVhv18L6lIxPI= MIME-Version: 1.0 Received: by 10.52.20.35 with SMTP id k3mr3976321vde.34.1323048799987; Sun, 04 Dec 2011 17:33:19 -0800 (PST) Sender: adrian.chadd@gmail.com Received: by 10.52.109.10 with HTTP; Sun, 4 Dec 2011 17:33:19 -0800 (PST) In-Reply-To: <7FF1FBB8-2A6B-49E1-88ED-E46ED23DAD87@lassitu.de> References: <7FF1FBB8-2A6B-49E1-88ED-E46ED23DAD87@lassitu.de> Date: Mon, 5 Dec 2011 09:33:19 +0800 X-Google-Sender-Auth: m_yjnEtZcK7V1knmV5Ovfp4-uhk Message-ID: From: Adrian Chadd To: Stefan Bethke Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Cc: freebsd-embedded@freebsd.org Subject: Re: ar71xx_gpio.c touches SPI_CS1 and 2? X-BeenThere: freebsd-embedded@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: Dedicated and Embedded Systems List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 05 Dec 2011 01:33:21 -0000 On 4 December 2011 21:59, Stefan Bethke wrote: >> I'm pretty sure the SPI flash is actually being talked to via >> bitbanged GPIO, rather than the actual ar71xx/ar91xx SPI interface. >> So those chip selects aren't strictly needed. > > I couldn't tell. =A0The register definitions in ar71xxreg.h seem to indic= ate that there is hardware support for SPI, and that CS1 and CS2 (but not C= S0) share the pins with GPIO, but looking at the code in ar71xx_spi.c seems= to do bit banging for transmit and register read for reception. =A0Does th= e SPI support only have a shift register for reception? I'm wrong. ar71xx_spi.c actually does use the SPI block. Ask me about that after mid-december. I have the atheros SoC datasheets; I just have no time to figure it out. Maybe ask ray@, he also has access to these datasheets now. (No we can't give them out. Yes, you can sign an NDA with Qualcomm Atheros to get access to some of this documentation.) > Hhm. > > How about the ar71xx_spi.c driver claiming CS0 and optionally CS1 and CS2= (again via hint?), and setting the GPIO function bits accordingly? =A0Or o= nly activate CS1 and CS2 if we have SPI bus children that claim them? Let's just have a hint that says "claim CS1 / claim CS2" for the ar71xx spi code. I think that'll be enough. We can then get rid of that function_enable call in ar71xx_gpio.c. The trick here is making sure we properly lock access to the function register? :) Adrian