Date: Thu, 30 Oct 2003 10:13:41 -0800 (PST) From: Juli Mallett <jmallett@FreeBSD.org> To: Perforce Change Reviews <perforce@freebsd.org> Subject: PERFORCE change 40844 for review Message-ID: <200310301813.h9UIDfnF055366@repoman.freebsd.org>
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http://perforce.freebsd.org/chv.cgi?CH=40844 Change 40844 by jmallett@jmallett_sprout on 2003/10/30 10:13:21 Nuke stuff which is meant to interact with fairly high-level bits of code which are: 1) Unused 2) Gross 3) Fairly NetBSD-geared. I totally want to get rid of locore.h... As a step in that direction, I've cut mips_subr down to just TLB stuff, which I mostly plan to rewrite in C using cpufunc stuff. Once that stuff is taken care of, just a few edge cases involving NetBSD code need rewritten to get rid of <machine/locore.h>. Affected files ... .. //depot/projects/mips/sys/mips/include/locore.h#9 edit .. //depot/projects/mips/sys/mips/mips/locore_mips3.S#11 edit .. //depot/projects/mips/sys/mips/mips/machdep.c#32 edit .. //depot/projects/mips/sys/mips/mips/mips_subr.S#12 edit Differences ... ==== //depot/projects/mips/sys/mips/include/locore.h#9 (text+ko) ==== @@ -37,58 +37,16 @@ int mips64_TLBUpdate(u_int, u_int); void mips64_TLBRead(int, struct tlb *); void mips64_wbflush(void); -void mips64_proc_trampoline(void); -void mips64_cpu_switch_resume(void); -void mips64_pagezero(caddr_t dst); - -uint32_t mips3_cp0_compare_read(void); -void mips3_cp0_compare_write(uint32_t); -uint32_t mips3_cp0_config_read(void); -void mips3_cp0_config_write(uint32_t); uint32_t mipsNN_cp0_config1_read(void); void mipsNN_cp0_config1_write(uint32_t); uint32_t mipsNN_cp0_config2_read(void); uint32_t mipsNN_cp0_config3_read(void); -uint32_t mips3_cp0_count_read(void); -void mips3_cp0_count_write(uint32_t); - -uint32_t mips3_cp0_wired_read(void); -void mips3_cp0_wired_write(uint32_t); - -/* - * A vector with an entry for each mips-ISA-level dependent - * locore function, and macros which jump through it. - * - * XXX the macro names are chosen to be compatible with the old - * XXX Sprite coding-convention names used in 4.4bsd/pmax. - */ -typedef struct { - void (*TBIA)(int); - void (*TBIAP)(int); - void (*TBIS)(vm_paddr_t); - int (*tlbUpdate)(u_int highreg, u_int lowreg); - void (*wbflush)(void); -} mips_locore_jumpvec_t; - -void mips_wait_idle(void); - -/* - * The "active" locore-fuction vector, and - */ -extern mips_locore_jumpvec_t mips_locore_jumpvec; -extern long *mips_locoresw[]; - #define MIPS_TBIA() mips64_TBIA(mips_num_tlb_entries) #define MIPS_TBIAP() mips64_TBIAP(mips_num_tlb_entries) #define MIPS_TBIS mips64_TBIS #define MachTLBUpdate mips64_TLBUpdate -#define proc_trampoline mips64_proc_trampoline - -#define CPU_IDLE (mips_locoresw[2]) - -/* cpu_switch_resume is called inside locore.S */ /* * CPU identification, from PRID register. ==== //depot/projects/mips/sys/mips/mips/locore_mips3.S#11 (text+ko) ==== @@ -182,93 +182,6 @@ .set pop END(mipsNN_cp0_config3_read) -LEAF(mips_wait_idle) - j mips_maybewait_idle - li t1, 1 -END(mips_wait_idle) - -LEAF(mips_idle) - j mips_maybewait_idle - move t1, zero -END(mips_idle) - -/* - * mips_maybewait_idle: - * - * When no processes are on the runq, cpu_switch branches to - * idle to wait for something to come ready. - * - * NOTE: This is really part of cpu_switch(), but defined here - * for kernel profiling. - * - * This version takes advantage of power-saving features on - * the QED RM52xx family of CPUs, and MIPS32 & MIPS64 CPUs, - * if t1 is non-zero. - */ -LEAF(mips_maybewait_idle) - ld t0, pcpup - sd zero, PC_CURTHREAD(t0) # set curthread NULL -#if defined(LOCKDEBUG) - jal sched_unlock_idle # release sched_lock - nop -#endif - li t0, (MIPS_INT_MASK | MIPS_SR_INT_IE) - mtc0 t0, MIPS_COP_0_STATUS # enable all interrupts - COP0_SYNC - nop - -#if XXX - /* Try to zero some free pages. */ - lw t0, uvm + UVM_PAGE_IDLE_ZERO - nop - beq t0, zero, 1f - nop - jal uvm_pageidlezero - nop -#endif -1: -#if XXX - lw t0, sched_whichqs # look for non-empty queue - bne t0, zero, 1f - nop -#endif - beq t1, zero, 1b - nop - wait - nop - nop - nop - b 1b - nop -1: -#if defined(LOCKDEBUG) - mtc0 zero, MIPS_COP_0_STATUS # disable all interrupts - COP0_SYNC - nop - nop - nop - nop - jal _C_LABEL(sched_lock_idle) # acquire sched_lock - nop -#if XXX - la ra, cpu_switch_queuescan - j ra - nop -#endif -#else - mtc0 zero, MIPS_COP_0_STATUS # disable all interrupts - COP0_SYNC - nop - nop - nop -#if XXX - la ra, cpu_switch_queuescan - j ra - nop -#endif -#endif -END(mips_maybewait_idle) - #if defined(DDB) || defined(KGDB) /* * setjmp(label_t *) ==== //depot/projects/mips/sys/mips/mips/machdep.c#32 (text+ko) ==== @@ -165,7 +165,6 @@ #include <machine/cpuinfo.h> #include <machine/cpuregs.h> #include <machine/hwfunc.h> -#include <machine/locore.h> #include <machine/md_var.h> #include <machine/mipsNN.h> #include <machine/pte.h> @@ -348,12 +347,7 @@ */ static void mips64_vector_init(void); -extern long *mips64_locoresw[]; - -mips_locore_jumpvec_t mips_locore_jumpvec; -long *mips_locoresw[3]; - struct pridtab { int cpu_cid; int cpu_pid; @@ -573,18 +567,6 @@ }; #define ncidnames (sizeof(cidnames) / sizeof(cidnames[0])) -/* - * MIPS64 locore function vector - */ -const mips_locore_jumpvec_t mips64_locore_vec = -{ - mips64_TBIA, - mips64_TBIAP, - mips64_TBIS, - mips64_TLBUpdate, - mips_wbflush, -}; - static void mips64_vector_install(vm_offset_t addr, char *begin, char *end) { @@ -630,12 +612,6 @@ mips64_vector_install(MIPS3_INTR_EXC_VEC, ExceptionVector, ExceptionVectorEnd); - /* - * Copy locore-function vector. - */ - memcpy(&mips_locore_jumpvec, &mips64_locore_vec, - sizeof(mips_locore_jumpvec_t)); - mips_icache_sync_all(); mips_dcache_wbinv_all(); @@ -770,19 +746,11 @@ mips64_TBIA(mips_num_tlb_entries); mips_wr_wired(MIPS3_TLB_WIRED_UPAGES); mips64_vector_init(); - memcpy(mips_locoresw, mips64_locoresw, sizeof(mips_locoresw)); break; default: printf("cpu_arch 0x%x: not supported\n", cpu_arch); cpu_halt(); } - - /* - * Install power-saving idle routines. - */ - if ((mips_cpu_flags & CPU_MIPS_USE_WAIT) && - !(mips_cpu_flags & CPU_MIPS_NO_WAIT)) - CPU_IDLE = (long *)mips_wait_idle; } /* ==== //depot/projects/mips/sys/mips/mips/mips_subr.S#12 (text+ko) ==== @@ -359,162 +359,6 @@ END(MIPSX(TLBRead)) /* - * mipsN_proc_trampoline() - * - * Arrange for a function to be invoked neatly, after a cpu_switch(). - * Call the service function with one argument, specified by the s0 - * and s1 respectively. There is no need register save operation. - */ -LEAF(MIPSX(proc_trampoline)) - addu sp, sp, -CALLFRAME_SIZ - jal ra, s0 - move a0, s1 - .set noat - /* - * Make sure to disable interrupts here, as otherwise - * we can take an interrupt *after* EXL is set, and - * end up returning to a bogus PC since the PC is not - * saved if EXL=1. - */ - mtc0 zero, MIPS_COP_0_STATUS # disable int - COP0_SYNC - nop # 3 op delay - nop - nop - li a0, MIPS_SR_EXL # set exception level - mtc0 a0, MIPS_COP_0_STATUS - COP0_SYNC - nop - nop - addu a1, sp, CALLFRAME_SIZ - /* REG_L a0, FRAME_SR(a1) */ - REG_L t0, FRAME_MULLO(a1) - REG_L t1, FRAME_MULHI(a1) - REG_L v0, FRAME_EPC(a1) - mtlo t0 - mthi t1 - _MTC0 v0, MIPS_COP_0_EXC_PC - COP0_SYNC - nop - move k1, a1 -#ifdef IPL_ICU_MASK - .set at - lw t0, FRAME_PPL(k1) - sw t0, md_imask - jal md_imask_update - nop - .set noat -#endif - REG_L AT, FRAME_AST(k1) - REG_L v0, FRAME_V0(k1) - REG_L v1, FRAME_V1(k1) - REG_L a0, FRAME_A0(k1) - REG_L a1, FRAME_A1(k1) - REG_L a2, FRAME_A2(k1) - REG_L a3, FRAME_A3(k1) - REG_L t0, FRAME_T0(k1) - REG_L t1, FRAME_T1(k1) - REG_L t2, FRAME_T2(k1) - REG_L t3, FRAME_T3(k1) - REG_L ta0, FRAME_TA0(k1) - REG_L ta1, FRAME_TA1(k1) - REG_L ta2, FRAME_TA2(k1) - REG_L ta3, FRAME_TA3(k1) - REG_L s0, FRAME_S0(k1) - REG_L s1, FRAME_S1(k1) - REG_L s2, FRAME_S2(k1) - REG_L s3, FRAME_S3(k1) - REG_L s4, FRAME_S4(k1) - REG_L s5, FRAME_S5(k1) - REG_L s6, FRAME_S6(k1) - REG_L s7, FRAME_S7(k1) - REG_L t8, FRAME_T8(k1) - REG_L t9, FRAME_T9(k1) - REG_L k0, FRAME_SR(k1) - REG_L gp, FRAME_GP(k1) - REG_L s8, FRAME_S8(k1) - REG_L ra, FRAME_RA(k1) - REG_L sp, FRAME_SP(k1) - mtc0 k0, MIPS_COP_0_STATUS - COP0_SYNC - nop - nop - eret - .set at -END(MIPSX(proc_trampoline)) - -/* - * void mipsN_cpu_switch_resume(struct lwp *newlwp) - * - * Wiredown the USPACE of newproc in TLB entry#0. Check whether target - * USPACE is already in another place of TLB before that, and make - * sure TBIS(it) in the case. - */ -LEAF_NOPROFILE(MIPSX(cpu_switch_resume)) - lw a1, TD_MD_UPTE_0(a0) # a1 = upte[0] - lw a2, TD_MD_UPTE_1(a0) # a2 = upte[1] - ld v0, TD_PROC(a0) # v0 = td->proc - ld v0, P_UAREA(v0) # va = v0->p_uarea - li s0, MIPS_KSEG2_START - blt v0, s0, resume - nop - - and s0, v0, PG_ODDPG - beq s0, zero, entry0 - nop - - PANIC("USPACE sat on odd page boundary") - -entry0: - _MTC0 v0, MIPS_COP_0_TLB_HI # VPN = va - COP0_SYNC - nop - nop - tlbp # probe VPN - COP0_SYNC - nop - nop - mfc0 s0, MIPS_COP_0_TLB_INDEX - nop - bltz s0, entry0set - sll s0, s0, 13 # PAGE_SHIFT + 1 - la s0, MIPS_KSEG0_START(s0) - _MTC0 s0, MIPS_COP_0_TLB_HI - COP0_SYNC - _MTC0 zero, MIPS_COP_0_TLB_LO0 - COP0_SYNC - _MTC0 zero, MIPS_COP_0_TLB_LO1 - COP0_SYNC - nop - nop - tlbwi - COP0_SYNC - nop - nop - _MTC0 v0, MIPS_COP_0_TLB_HI # set VPN again - COP0_SYNC -entry0set: - mtc0 zero, MIPS_COP_0_TLB_INDEX # TLB entry #0 - COP0_SYNC - or a1, PG_G - _MTC0 a1, MIPS_COP_0_TLB_LO0 # upte[0] | PG_G - COP0_SYNC - or a2, PG_G - _MTC0 a2, MIPS_COP_0_TLB_LO1 # upte[1] | PG_G - COP0_SYNC - nop - nop - tlbwi # set TLB entry #0 - COP0_SYNC - nop - nop - -resume: - j ra - nop -END(MIPSX(cpu_switch_resume)) - -/* * void mipsN_TBIS(vaddr_t va) * * Invalidate a TLB entry which has the given vaddr and ASID if found. @@ -680,30 +524,3 @@ mtc0 v1, MIPS_COP_0_STATUS # restore status register COP0_SYNC # XXXX - not executed!! END(MIPSX(TBIA)) - -LEAF(MIPSX(pagezero)) - li a1, NBPG >> 6 - -1: sd zero, 0(a0) # try to miss cache first - sd zero, 32(a0) - subu a1, 1 - sd zero, 16(a0) - sd zero, 48(a0) - sd zero, 8(a0) # fill in cache lines - sd zero, 40(a0) - sd zero, 24(a0) - sd zero, 56(a0) - bgtz a1, 1b - addu a0, 64 - - j ra - nop -END(MIPSX(pagezero)) - - .data - - .globl MIPSX(locoresw) -MIPSX(locoresw): - .dword MIPSX(cpu_switch_resume) - .dword MIPSX(proc_trampoline) - .dword mips_idle
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