From owner-freebsd-mips@FreeBSD.ORG Sat Jul 17 18:36:00 2010 Return-Path: Delivered-To: freebsd-mips@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id 8030F10656FF; Sat, 17 Jul 2010 18:36:00 +0000 (UTC) (envelope-from c.jayachandran@gmail.com) Received: from mail-vw0-f54.google.com (mail-vw0-f54.google.com [209.85.212.54]) by mx1.freebsd.org (Postfix) with ESMTP id 9CC2A8FC21; Sat, 17 Jul 2010 18:35:59 +0000 (UTC) Received: by vws19 with SMTP id 19so4459105vws.13 for ; Sat, 17 Jul 2010 11:35:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:mime-version:received:received:in-reply-to :references:date:message-id:subject:from:to:cc:content-type; bh=DMZT54iP6ChPCXLSR9L95jYbP9VHiYNZqnQEVRQmsMY=; b=pQ3XCsTRHbQGTFrHMFUfQGLbkMlWDMZ+aUD6QbYjN4pefMrscxz/7tNRGga3ZFXerW Kf2f/BmumIIAGytHVk3F/ANss124fnO8n/B0i5G/JsEA0UDLupFwy7HAwx30+GWWReKo 8A+vRTEqzKCIckmsOqEoKJGsrIOAd/gsAfGhA= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type; b=MTA86ZAfWy3fVee+oHWS3/Tn1xEJi91c3vbHbGFMIR190aR5Igytq0KWYudDKI9Mg3 jOSfoKSSlnHcprPLW9qsLUftaH0cmqyRifDvgIyC0dZzv1OvWAGcV0rNqcswoOBorEJL 8gvhGLPLGYubDBFu3tijljBAF80Ee7Ez/VmgU= MIME-Version: 1.0 Received: by 10.220.60.203 with SMTP id q11mr1483399vch.28.1279391758920; Sat, 17 Jul 2010 11:35:58 -0700 (PDT) Received: by 10.220.188.138 with HTTP; Sat, 17 Jul 2010 11:35:58 -0700 (PDT) In-Reply-To: <4C41B4CF.6080409@FreeBSD.org> References: <4C41A248.8090605@FreeBSD.org> <4C41B4CF.6080409@FreeBSD.org> Date: Sun, 18 Jul 2010 00:05:58 +0530 Message-ID: From: "Jayachandran C." To: Alexander Motin Content-Type: text/plain; charset=ISO-8859-1 Cc: Neel Natu , freebsd-mips@freebsd.org Subject: Re: [RFC] Event timers on MIPS X-BeenThere: freebsd-mips@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: Porting FreeBSD to MIPS List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 17 Jul 2010 18:36:00 -0000 On Sat, Jul 17, 2010 at 7:19 PM, Alexander Motin wrote: > Jayachandran C. wrote: >> 2010/7/17 Alexander Motin : >>> I've made a patch, updating MIPS timer code (except RMI) to utilize new >>> MI event timer infrastructure. I've successfully built QEMU and XLR >>> kernels with the patch. Unluckily I can't test how it works, unless >>> somebody teach me how to cook QEMU to run it. I also haven't ported RMI >>> timers drivers, as I am not sure how that hardware is intended to work. >>> >>> Patch for HEAD can be found here: >>> http://people.freebsd.org/~mav/timers_mips.patch >>> >>> Could somebody falimiar with MIPS review/test my patch and extend it to >>> RMI hardware? >> >> XLR uses an on-chip PIC clock (running at 66MHz) for cpu 0 and >> count/compare clock (running at CPU freq) for the other CPUs, hope >> this is supported with the new code. > > I suppose that one type of timers should run on all CPUs (either one > timer per CPU, or one timer for all of them + IPI for distribution). > Theoretically you can implement "single" per-CPU timer implemented in > different fashion for different CPUs, though I don't understand why it > is needed. If these timers are independent, I would register every of > them as-is: on-chip PIC clock as global timer (infrastructure will > automatically manage rebroadcasting it's events via IPIs) and per-CPU > comparators as another per-CPU timer. This give independent hardclock > and statclock for less aliased time accounting. > >> Other than that, I should be able to merge the code into XLR specific >> rmi/tick.c rmi/clock.c, if it works on other MIPS platforms. > > rmi/tick.c looks somewhat strange to me, registering timecounter with > the same "MIPS32" name, but with different meaning. On XLR we would like to use the count/compare which is faster but less accurate on all cpus - we can have upto 32 cpus now. We also have a PIC which can provide a better timestamp and timer interrupts. This PIC timestamp can be read from all CPUs but the timer interrupt can be delivered to just one CPU at a time. I think this is how we ended up with the current implementation, but any suggestions on how to improve this is welcome. Thanks, JC.