From owner-freebsd-current@FreeBSD.ORG Sun Oct 8 20:58:41 2006 Return-Path: X-Original-To: freebsd-current@freebsd.org Delivered-To: freebsd-current@freebsd.org Received: from mx1.FreeBSD.org (mx1.freebsd.org [216.136.204.125]) by hub.freebsd.org (Postfix) with ESMTP id 1E76C16A407 for ; Sun, 8 Oct 2006 20:58:41 +0000 (UTC) (envelope-from ivoras@fer.hr) Received: from ls405.htnet.hr (ls405.t-com.hr [195.29.150.135]) by mx1.FreeBSD.org (Postfix) with ESMTP id 0193543D60 for ; Sun, 8 Oct 2006 20:58:35 +0000 (GMT) (envelope-from ivoras@fer.hr) Received: from ls422.t-com.hr (ls422.t-com.hr [195.29.150.237]) by ls405.htnet.hr (Postfix) with ESMTP id CCDC4144981; Sun, 8 Oct 2006 22:58:33 +0200 (CEST) Received: from ls422.t-com.hr (localhost.localdomain [127.0.0.1]) by ls422.t-com.hr (Qmlai) with ESMTP id B5035C90048; Sun, 8 Oct 2006 22:58:33 +0200 (CEST) X-Envelope-Sender: ivoras@fer.hr Received: from [10.0.0.100] (83-131-108-115.adsl.net.t-com.hr [83.131.108.115])by ls422.t-com.hr (Qmlai) with ESMTP id 5E0751308030; Sun, 8 Oct 2006 22:58:32 +0200 (CEST) Message-ID: <4529667D.8070108@fer.hr> Date: Sun, 08 Oct 2006 22:58:37 +0200 From: Ivan Voras User-Agent: Thunderbird 1.5.0.7 (Windows/20060909) MIME-Version: 1.0 To: Kip Macy References: <2fd864e0610080423q7ba6bdeal656a223e662a5d@mail.gmail.com> <2006 10082011.53649.davidxu@freebsd.org> <20061008135031.G83537@demos.bsdclusters.com> In-Reply-To: <20061008135031.G83537@demos.bsdclusters.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-imss-version: 2.043 X-imss-result: Passed X-imss-scores: Clean:99.90000 C:2 M:3 S:5 R:5 X-imss-settings: Baseline:1 C:1 M:1 S:1 R:1 (0.0000 0.0000) Cc: freebsd-current@freebsd.org Subject: Re: [PATCH] MAXCPU alterable in kernel config - needs testers X-BeenThere: freebsd-current@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: Discussions about the use of FreeBSD-current List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 08 Oct 2006 20:58:41 -0000 Kip Macy wrote: > It will only cover the single chip Niagara 2 boxes. Oh right, they'll doing multi chips in Niagara 2 :) Go Sun :) Still, single T2 chips should be more common, so I'd guess it will pay to optimize for that case. (For the rest of the audience: Niagara 1 has 32 logical CPUs and supports only one physical CPU/socket; Niagara 2 will have 64 logical CPUs and support > 1 CPUs/sockets; so a 2 socket Niagara 2 box will have 128 logical processors! Cue SciFi music...) Any word on how will they handle migration of threads across sockets (or will it be OS's job)? Judging from T1 architecture, I think such event would create a very large performance penalty, but I'm not an expert.