Date: Wed, 30 Aug 1995 09:06:20 +0930 (CST) From: Michael Smith <msmith@atrad.adelaide.edu.au> To: bde@zeta.org.au (Bruce Evans) Cc: leo@lisa.rur.com, rgrimes@gndrsh.aac.dev.com, freebsd-hackers@FreeBSD.ORG, jbryant@argus.iadfw.net, rashid@haven.ios.com Subject: Re: S.O.S -2.1Stable and ASUSP54TP4 Message-ID: <199508292336.JAA27015@genesis.atrad.adelaide.edu.au> In-Reply-To: <199508292149.HAA02386@godzilla.zeta.org.au> from "Bruce Evans" at Aug 30, 95 07:49:56 am
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Bruce Evans stands accused of saying: > > >And to state my reason for agreement that parity is a ``itsy-bitsy comfort'', > >think about the fact that 80% of your memory access are going to a L2 > >cache that has never had parity on it, yet has a same FIT rate as the > >main memory system. Basically your more likely today to take a single > >bit error in your cache as you are in main memory :-(. > > Is there anything to detect or correct errors in the registers or > control logic? They're not susceptible in the same way (and static memories are much less susceptible than dynamic memories). The #1 cause of single-bit errors are charged particles resulting from radioactive decay in the chip packaging materials. (One reason why ceramic-package memories are almost extinct). DRAMs, which depend on the charge on a tiny capacitor, are vulnerable to having this charge corrupted by a small storm of such particles. Static memories don't use this technique, and are thus resistant to this form of corruption. > Bruce -- ]] Mike Smith, Software Engineer msmith@atrad.adelaide.edu.au [[ ]] Genesis Software genesis@atrad.adelaide.edu.au [[ ]] High-speed data acquisition and [[ ]] realtime instrument control (ph/fax) +61-8-267-3039 [[ ]] My car has "demand start" -Terry Lambert UNIX: live FreeBSD or die! [[
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