From owner-freebsd-mips@FreeBSD.ORG Fri Apr 5 14:57:07 2013 Return-Path: Delivered-To: freebsd-mips@freebsd.org Received: from mx1.freebsd.org (mx1.FreeBSD.org [8.8.178.115]) by hub.freebsd.org (Postfix) with ESMTP id D659BDEA for ; Fri, 5 Apr 2013 14:57:07 +0000 (UTC) (envelope-from pkelsey@gmail.com) Received: from mail-bk0-x232.google.com (mail-bk0-x232.google.com [IPv6:2a00:1450:4008:c01::232]) by mx1.freebsd.org (Postfix) with ESMTP id 6CE80B3E for ; Fri, 5 Apr 2013 14:57:07 +0000 (UTC) Received: by mail-bk0-f50.google.com with SMTP id jg1so2098193bkc.23 for ; Fri, 05 Apr 2013 07:57:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=mime-version:x-received:sender:in-reply-to:references:date :x-google-sender-auth:message-id:subject:from:to:cc:content-type; bh=2i/zNAcmQtaDWCWXg5hyuVQcpuTQkvENr3JUNA/GUPE=; b=yfebl3QT31GXiInnhLoVIOahpORootIodyWUV3yk3is477GRbGsKB5YnzzA5k+wsqr 23t1voXMxyv+Eut6xUERRmnQZhx2Ud/Ee8VhkaWMbe61ZEuByG/J2aspDvRN5Ffzn0e8 kD4oiIBuz3KYJ+caWRh6ZG/xahJ5HjJ6fi57eAl8xclT2yXu4akrAJI6QUAArxgEJdqa HpZYWyad4QeseUD6TCeb3Ay+hQAyHk0komHgDKHvBc7rQVW65Tu5P15pyZqFVEoSCS0H dx1NvKN7OZunnE0F2h0ECrr5PiirBuoPZKeQ18paAjmU/+HklQaKOqAKnyTbAR2GIrBr 0YpQ== MIME-Version: 1.0 X-Received: by 10.205.134.3 with SMTP id ia3mr7035326bkc.92.1365173826263; Fri, 05 Apr 2013 07:57:06 -0700 (PDT) Sender: pkelsey@gmail.com Received: by 10.204.128.213 with HTTP; Fri, 5 Apr 2013 07:57:06 -0700 (PDT) In-Reply-To: References: Date: Fri, 5 Apr 2013 10:57:06 -0400 X-Google-Sender-Auth: QbCXkmcgyCc7NKf-bIyMZxBOkFU Message-ID: Subject: Re: [PATCH] MMC/SD SPI-mode driver From: Patrick Kelsey To: Dmytro Content-Type: text/plain; charset=ISO-8859-1 Cc: freebsd-mips@freebsd.org X-BeenThere: freebsd-mips@freebsd.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: Porting FreeBSD to MIPS List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 05 Apr 2013 14:57:07 -0000 On Thu, Apr 4, 2013 at 11:11 PM, Dmytro wrote: > Thank you Patrick for the detailed answers. > Given the platform processors Atheros, it is safe to say that all line > ath79 (AR71XX/AR724X/AR913X SoCs) - SPI generic and has not changed > even in the new generations of this CPUs. > Working in OpenWRT, I can say that reading speed/CPU load is about the > same as yours - slow. > But I did not quite understand how to implemented the function of fast > reading for NOR flash memory in driver (m25p80.c). > Reading speed of NOR flash-memory about 3 MB/Without a full load CPU. > I understand that it is sent to a specific command/register for a fast > read is also SPI uses the buffer of NOR chip . > However, at what level SPI controller is programmed for increasing > speed - is not clear. > http://dioptimizer.narod.ru/files/spi-ath79.c > My understanding is that in the AR71xx (and possibly other related Atheros SoCs), the boot flash can be read through memory mapped access to a region starting at the reset address, as this is how booting from a serial flash is accomplished. In that scenario, the SPI controller will be translating each read access into an SPI bus transaction that will produce the desired data from the flash. Since the hardware is performing the SPI signalling, you wouldn't have the CPU overhead of bitbanging each SPI bit out. Performance would still be limited by the value set in the SPI clock divider register (which controls the bit times on the wire) and the speed of the clock that runs the SPI unit itself. -Patrick