Date: Sat, 6 Jan 2018 13:30:29 +1100 From: Andrew Reilly <areilly@bigpond.net.au> To: blubee blubeeme <gurenchan@gmail.com> Cc: "Klaus P. Ohrhallinger" <k@7he.at>, FreeBSD current <freebsd-current@freebsd.org> Subject: Re: Intel CPU design flaw - FreeBSD affected? // disabling _R_DTSC Message-ID: <20180106015852.GA46842@Zen.ac-r.nu> In-Reply-To: <CALM2mEk1Dtd9f0gc6pScjVizr-2j5N6YRXiJM%2BDqm5maejd5NQ@mail.gmail.com> References: <9dda0496-be16-35c6-6c45-63d03b218ccb@protected-networks.net> <18376c97-3c0d-49c8-9483-96b95a84f3f1@7he.at> <52b2f48c-332c-8984-838f-4902da0ebc81@7he.at> <CALM2mEk1Dtd9f0gc6pScjVizr-2j5N6YRXiJM%2BDqm5maejd5NQ@mail.gmail.com>
next in thread | previous in thread | raw e-mail | index | archive | help
On Fri, Jan 05, 2018 at 02:27:40AM +0800, blubee blubeeme wrote: > I'd love to see if RISC-V is vulnerable to this? > > I think they are in the best position to capitalize on this clusterfk... It's a micro-architecture flaw, not an instruction set flaw, so just as for ARM and amd64, it will depend on the specific version. The only RISC-V hardware that I'm aware of is in-order (no speculation) so unlikely to be affected. There aren't any data-centre-scale RISC-V systems yet, but some are being worked-on. Will be interesting to see if they suddenly push out roadmaps while they go back to re-design to avoid this... Cheers, Andrew
Want to link to this message? Use this URL: <https://mail-archive.FreeBSD.org/cgi/mid.cgi?20180106015852.GA46842>