From owner-freebsd-arm@FreeBSD.ORG Wed Apr 4 09:37:17 2007 Return-Path: X-Original-To: freebsd-arm@freebsd.org Delivered-To: freebsd-arm@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [69.147.83.52]) by hub.freebsd.org (Postfix) with ESMTP id 2B47616A403 for ; Wed, 4 Apr 2007 09:37:17 +0000 (UTC) (envelope-from ticso@cicely12.cicely.de) Received: from raven.bwct.de (raven.bwct.de [85.159.14.73]) by mx1.freebsd.org (Postfix) with ESMTP id CA45713C44B for ; Wed, 4 Apr 2007 09:37:16 +0000 (UTC) (envelope-from ticso@cicely12.cicely.de) Received: from cicely5.cicely.de ([10.1.1.7]) by raven.bwct.de (8.13.4/8.13.4) with ESMTP id l349b81k019697; Wed, 4 Apr 2007 11:37:08 +0200 (CEST) (envelope-from ticso@cicely12.cicely.de) Received: from cicely12.cicely.de (cicely12.cicely.de [10.1.1.14]) by cicely5.cicely.de (8.13.4/8.13.4) with ESMTP id l349arm4060563 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Wed, 4 Apr 2007 11:36:53 +0200 (CEST) (envelope-from ticso@cicely12.cicely.de) Received: from cicely12.cicely.de (localhost [127.0.0.1]) by cicely12.cicely.de (8.13.4/8.13.3) with ESMTP id l349aqfL004778; Wed, 4 Apr 2007 11:36:52 +0200 (CEST) (envelope-from ticso@cicely12.cicely.de) Received: (from ticso@localhost) by cicely12.cicely.de (8.13.4/8.13.3/Submit) id l349aqFt004777; Wed, 4 Apr 2007 11:36:52 +0200 (CEST) (envelope-from ticso) Date: Wed, 4 Apr 2007 11:36:52 +0200 From: Bernd Walter To: Krassimir Slavchev Message-ID: <20070404093651.GY80382@cicely12.cicely.de> References: <20070403154858.GR80382@cicely12.cicely.de> <46135EDC.30700@bulinfo.net> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <46135EDC.30700@bulinfo.net> X-Operating-System: FreeBSD cicely12.cicely.de 5.4-STABLE alpha User-Agent: Mutt/1.5.9i X-Spam-Status: No, score=-4.4 required=5.0 tests=ALL_TRUSTED=-1.8, BAYES_00=-2.599 autolearn=ham version=3.1.7 X-Spam-Checker-Version: SpamAssassin 3.1.7 (2006-10-05) on cicely12.cicely.de Cc: Bernd Walter , freebsd-arm@freebsd.org, ticso@cicely.de Subject: Re: adding 16550 UART to RM9200 X-BeenThere: freebsd-arm@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list Reply-To: ticso@cicely.de List-Id: Porting FreeBSD to the StrongARM Processor List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 04 Apr 2007 09:37:17 -0000 On Wed, Apr 04, 2007 at 11:16:28AM +0300, Krassimir Slavchev wrote: > You may look at this: > http://www.nxp.com/news/content/file_1194.html Exar has something similar with the XR20M117x/XR20V117x The problem with IIC is that it is way to slow (max 400kbps) and is to be shared with 48 UARTS, which even invalidates the full data rate. You can't even run a single UART at 230kbps. Plus IIC is quite expensive in respect of CPU time on the RM9200. IIC is what I do right now - an USB master electronic for ubser(4) plus multiple IIC connected ATMEGA8 controller doing a few software UART at 9600bps each. SPI may be fast enough but requires a select line per UART, which of course can be done via 6 to 64 decoder. SPI works good for bulk transfers on the RM9200, but since we are likely doing small transfers it is not very efficient. And it requires a complete new set of drivers. Additionally the 16C554 is available from multiple vendors and much easier to source in small volume than the IIC/SPI chips. If that wouldn't be a reason I would have selected the Exar XR16L788, which is a 8 channel 16550 compatible UART with 64 Byte buffers and an integraded ILR. > Bernd Walter wrote: > >I plan to add up to 48 16550 UART to an RM9200 system. > >It should be done with 16C554 chips - so I only have 16 byte FiFo. > >I would like to avoid using 64 byte FiFo chips, but those are pin > >compatible, so things are changeable in case. > >Likely most of the ports are doing low volume and I hope this will > >be Ok. > >They will be addressed via NCS2 space. > >Most of the external interrupts are not available because of > >unfortunate multiplexing with other required signals, so I have to > >attach them all to IRQ0. > >The interrupt will be level configured by firmware. > >And the NCS2 waitstates and buswidth will be configured by firmware > >as well. > > > >However some question points are still left: > > > >- How can I attach our uart(4) driver to the chips? > >It will likely addressed with: > >UART0 0x30000000 - 0x30000007 IRQ0 > >UART1 0x30000008 - 0x3000000f IRQ0 > >UART2 0x30000010 - 0x30000017 IRQ0 > >UART3 0x30000018 - 0x3000001f IRQ0 > >UART4 0x30000020 - 0x30000027 IRQ0 > >UART5 0x30000028 - 0x3000002f IRQ0 > >[...] > >UART47 0x30000170 - 0x30000177 IRQ0 > >UART48 0x30000178 - 0x3000017f IRQ0 > > > >- I would like to use a 14,7456MHz xtal > >How can I tell uart(4) the frequency? > > > >- How can I configure NCS2 range as being uncacheable? > >I asume this has to be done somehow in the kernel. -- B.Walter http://www.bwct.de http://www.fizon.de bernd@bwct.de info@bwct.de support@fizon.de