From owner-freebsd-hackers Fri Sep 17 12: 7:15 1999 Delivered-To: freebsd-hackers@freebsd.org Received: from lestat.nas.nasa.gov (lestat.nas.nasa.gov [129.99.33.127]) by hub.freebsd.org (Postfix) with ESMTP id 400961582E for ; Fri, 17 Sep 1999 12:05:25 -0700 (PDT) (envelope-from thorpej@lestat.nas.nasa.gov) Received: from lestat (localhost [127.0.0.1]) by lestat.nas.nasa.gov (8.8.8/8.6.12) with ESMTP id MAA18944; Fri, 17 Sep 1999 12:05:20 -0700 (PDT) Message-Id: <199909171905.MAA18944@lestat.nas.nasa.gov> To: Mohit Aron Cc: freebsd-hackers@FreeBSD.ORG Subject: Re: TLB miss handler for alpha running FreeBSD-4.0 Reply-To: Jason Thorpe From: Jason Thorpe Date: Fri, 17 Sep 1999 12:05:20 -0700 Sender: owner-freebsd-hackers@FreeBSD.ORG Precedence: bulk X-Loop: FreeBSD.ORG On Thu, 16 Sep 1999 23:10:21 -0500 (CDT) Mohit Aron wrote: ...well, I'm speaking from the NetBSD perspective, but it's the same in FreeBSD, because both use the OSF/1 PALcode... > as I understand it, TLB misses on the alpha are handled by the > software (as opposed to x86 where they are handled in hardware). Can someone They're handled by software, but not the operating system software (at least not under the OSF/1 PALcode). TLB misses are serviced by the PALcode, which presents a 3-level page table interface to the operating system. > help me with the FreeBSD code. I'm trying to locate the kernel code that > implements the TLB handler. I'd appreciate if someone can tell me how the > control is given to the software (i.e. what trap is generated), how the > handler is called and finally how does the control return back. Thanks, You should start by reading the `Alpha AXP Architecture Reference Manual', which is in the Third Edition now, I believe. It will describe to you in detail the interface the operating system has to the processor. -- Jason R. Thorpe To Unsubscribe: send mail to majordomo@FreeBSD.org with "unsubscribe freebsd-hackers" in the body of the message