From owner-svn-src-all@FreeBSD.ORG Mon Nov 8 07:54:25 2010 Return-Path: Delivered-To: svn-src-all@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id 3A3E81065780; Mon, 8 Nov 2010 07:54:25 +0000 (UTC) (envelope-from kevlo@FreeBSD.org) Received: from svn.freebsd.org (svn.freebsd.org [IPv6:2001:4f8:fff6::2c]) by mx1.freebsd.org (Postfix) with ESMTP id 28DF78FC18; Mon, 8 Nov 2010 07:54:25 +0000 (UTC) Received: from svn.freebsd.org (localhost [127.0.0.1]) by svn.freebsd.org (8.14.3/8.14.3) with ESMTP id oA87sPFB017986; Mon, 8 Nov 2010 07:54:25 GMT (envelope-from kevlo@svn.freebsd.org) Received: (from kevlo@localhost) by svn.freebsd.org (8.14.3/8.14.3/Submit) id oA87sPvp017984; Mon, 8 Nov 2010 07:54:25 GMT (envelope-from kevlo@svn.freebsd.org) Message-Id: <201011080754.oA87sPvp017984@svn.freebsd.org> From: Kevin Lo Date: Mon, 8 Nov 2010 07:54:25 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org X-SVN-Group: head MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Cc: Subject: svn commit: r214972 - head/sys/arm/include X-BeenThere: svn-src-all@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: "SVN commit messages for the entire src tree \(except for " user" and " projects" \)" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 08 Nov 2010 07:54:25 -0000 Author: kevlo Date: Mon Nov 8 07:54:24 2010 New Revision: 214972 URL: http://svn.freebsd.org/changeset/base/214972 Log: Intel IXP425 SoC is based on the ARMv5TE architecture MFC after: 3 days Modified: head/sys/arm/include/cpuconf.h Modified: head/sys/arm/include/cpuconf.h ============================================================================== --- head/sys/arm/include/cpuconf.h Mon Nov 8 03:08:01 2010 (r214971) +++ head/sys/arm/include/cpuconf.h Mon Nov 8 07:54:24 2010 (r214972) @@ -70,7 +70,7 @@ */ #if (defined(CPU_ARM7TDMI) || defined(CPU_ARM8) || defined(CPU_ARM9) || \ defined(CPU_SA110) || defined(CPU_SA1100) || defined(CPU_SA1110) || \ - defined(CPU_IXP12X0) || defined(CPU_XSCALE_IXP425) || defined(CPU_FA526)) + defined(CPU_IXP12X0) || defined(CPU_FA526)) #define ARM_ARCH_4 1 #else #define ARM_ARCH_4 0 @@ -79,7 +79,8 @@ #if (defined(CPU_ARM9E) || defined(CPU_ARM10) || \ defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \ defined(CPU_XSCALE_80219) || defined(CPU_XSCALE_81342) || \ - defined(CPU_XSCALE_PXA2X0) || defined(CPU_FA626TE)) + defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) || \ + defined(CPU_FA626TE)) #define ARM_ARCH_5 1 #else #define ARM_ARCH_5 0