From owner-freebsd-hackers Wed Dec 12 6:10:23 2001 Delivered-To: freebsd-hackers@freebsd.org Received: from srv1.cosmo-project.de (srv1.cosmo-project.de [213.83.6.106]) by hub.freebsd.org (Postfix) with ESMTP id 8BF4837B41B; Wed, 12 Dec 2001 06:10:17 -0800 (PST) Received: (from uucp@localhost) by srv1.cosmo-project.de (8.11.0/8.11.0) with UUCP id fBCEA0U82114; Wed, 12 Dec 2001 15:10:01 +0100 (CET) Received: from mail.cicely.de (cicely20.cicely.de [10.1.1.22]) by cicely5.cicely.de (8.12.1/8.12.1) with ESMTP id fBCE9ftx014021; Wed, 12 Dec 2001 15:09:41 +0100 (CET)?g (envelope-from ticso@cicely8.cicely.de) Received: from cicely8.cicely.de (cicely8.cicely.de [10.1.2.10]) by mail.cicely.de (8.11.0/8.11.0) with ESMTP id fBCE9eW08266; Wed, 12 Dec 2001 15:09:40 +0100 (CET) Received: (from ticso@localhost) by cicely8.cicely.de (8.11.6/8.11.6) id fBCE9UD18410; Wed, 12 Dec 2001 15:09:30 +0100 (CET) (envelope-from ticso) Date: Wed, 12 Dec 2001 15:09:28 +0100 From: Bernd Walter To: Terry Lambert Cc: Warner Losh , Danny Braniss , Mike Smith , freebsd-hackers@FreeBSD.ORG Subject: Re: irq Message-ID: <20011212150928.F15654@cicely8.cicely.de> References: <3C1614D5.B5C3B4C5@mindspring.com> <200112120516.fBC5GJM33101@harmony.village.org> <3C17393B.8297E824@mindspring.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <3C17393B.8297E824@mindspring.com> User-Agent: Mutt/1.3.23i X-Operating-System: FreeBSD cicely8.cicely.de 5.0-CURRENT i386 Sender: owner-freebsd-hackers@FreeBSD.ORG Precedence: bulk List-ID: List-Archive: (Web Archive) List-Help: (List Instructions) List-Subscribe: List-Unsubscribe: X-Loop: FreeBSD.ORG On Wed, Dec 12, 2001 at 03:02:19AM -0800, Terry Lambert wrote: > How is setting a local register when an interrupt is triggered > antithetical to such cards working? I know of several network > cards where I've personally hacked on the driver that have such > a register. > > It's not possbile to take a shared interrupt and not run the ISR, > but it's possible for the ISR to check the register and decide on > that basis, rather than on data availability, that it will or will > not do work. > > I think that everyone now "gets" that PCI interrupts are like > signals, in that they are persistant conditions, so more than one > card asserting them doesn't change the fact that "an interrupt" > was asserted, and there's no way to tell _from the interrupt_ > which cards did or did not assert it in the first place. But we > are talking about an extra hardware register on the card that the > card sets when it asserts an interrupt, so an ISR can look to ask > the card "did you assert an interrupt?" and decide not to process > if the answer is "no". > > The Tigon II interrupt sharing in fact depends on this, or when > you had two Tigon II cards, you migh spend the rest of eternity in > the ISR. I never understood why the PCI-bus is not a interupt vector design. -- B.Walter COSMO-Project http://www.cosmo-project.de ticso@cicely.de Usergroup info@cosmo-project.de To Unsubscribe: send mail to majordomo@FreeBSD.org with "unsubscribe freebsd-hackers" in the body of the message