Date: Wed, 7 Aug 2019 18:26:32 +0000 (UTC) From: Emmanuel Vadot <manu@FreeBSD.org> To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-stable@freebsd.org, svn-src-stable-12@freebsd.org Subject: svn commit: r350687 - in stable/12/sys: arm64/conf arm64/rockchip arm64/rockchip/clk conf dev/mmc/host Message-ID: <201908071826.x77IQW1A048156@repo.freebsd.org>
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Author: manu Date: Wed Aug 7 18:26:32 2019 New Revision: 350687 URL: https://svnweb.freebsd.org/changeset/base/350687 Log: MFC r341381-r341383, r341385, r343950, r344527, r344576-r344580, r344585, r344589-r344590, r344623, r344626-r344627 r341381: arm64: rockchip: Add RK3399_CLK_PLL PLLs on the RK3399 are different than the ones on the RK3328. Add a new type and some dedicated recalc and set_freq functions. Rename the RK3328 dedicated rk_clk_pll function with rk3328_ prefix. r341382: arm64/rockchip: add RK3399 support Add CRU (Clock and Reset Unit) driver for RK3399. Add support in rk_pinctrl driver. Submitted by: Greg V <greg@unrelenting.technology> (Original version) Differential Revision: https://reviews.freebsd.org/D16732 r341383: arm64: rockchip: rk_i2c: Use correct clock While here add RK3399 support and call clk_set_assigned to set the correct clock set in the DTS. r341385: arm64: rockchip: rk805: Add basic support for RK808 PMIC RK808 PMIC is the companion chip for RK3399 SoC. Add basic regulator support in RK805 since they are similar. r343950: arm64: Fix compile when removing SOC_ROCKCHIP_* options Make every rockchip file depend on the multiple soc_rockchip options While here make rk_i2c and rk_gpio depend on their device options. Reported by: sbruno r344527: arm64: rockchip: clk: Set the write mask when setting the clock mux RockChip clocks have a write mask in the upper 16bits of the mux register which wasn't set in the set_mux function. Also the wrong parent was tested instead of the real current one, when switch parent, test with the current one before. Pointy Hat: manu r344576: arm64: rockchip: clk: rk_clk_composite: Properly use the mask bits RockChip clocks register have a write mask in the upper 16 bits, if a 1 is present the corresponding bit in the lower 16 ones is set. Use this instead of always setting the mask to 0xFFFF0000. This avoids a read of the register. While here add some debug printf useful for debuging clock problems r344577: arm64: rockchip: clk: ARM CLK improvement RockChip clocks register have a write mask in the upper 16 bits, if a 1 is present the corresponding bit in the lower 16 ones is set. Use this instead of always setting the mask to 0xFFFF0000. This avoids a read of the register. While here set the parent after changing its freqeuncy, this reduce the time between changing the parent and changing the divider for the arm clock. r344578: arm64: rockchip: rk3328_pll: Multiple improvement RockChip clocks register have a write mask in the upper 16 bits, if a 1 is present the corresponding bit in the lower 16 ones is set. Use this instead of always setting the mask to 0xFFFF0000. This avoids a read of the register. While here, when switching PLL frequency, first switch it to slow mode. When set to slow mode the PLL clock will be the external oscillator. Changing the PLL parameters while its output is used can cause hang (sometimes). r344579: arm64: rockchip: rk805: Add LDO regulators Add the 3 LDO regulator found in the RK805 Power Management IC. r344580: arm64: rockchip: rk805: Map the regulator No map function was provided before so every regulator lookup resolved the regulator with id 1, as it uses the default mapper, which is wrong. Correctly map the regulators. While here remove some debug printfs and make them disable by default. r344585: arm64: rockchip: rk_pinctrl: Fix two banks in RK3328 The last two banks don't have 3 bits for the pin function but only 2. This fixes eMMC on the Rock64. r344589: arm64: rockchip: rk3399_pll: Switch to slow mode when changing the freq Like r344578 but for RK3399. This solve some hangs when switching between frequency. r344590: arm64: rockchip: rk3399_pll: Fix copy paste RK3399 PLLs don't have mode_reg, use the correct register. r344623: arm64: rockchip: clk_pll: Multiple improvement Remove the mode_val from the clock definition as it's a bit unreadable. Use mode_shift to represent which bit control the mode in the register. Simplify some case where we can avoid a register read before changing it. Set the PLL back to normal mode after the PLL have stabilized. Discussed with: mmel r344626: arm64: rockchip: rk3399_clk: Add sd clock definitions r344627: mmc: dwmmc: Match on "rockchip,rk3288-dw-mshc" compatible This is the common denominator for rockchip compatible from RK3288 to RK3399. The other compatible are generally present in the DTS but the controllers are the same. Added: stable/12/sys/arm64/rockchip/clk/rk3399_cru.c - copied, changed from r341383, head/sys/arm64/rockchip/clk/rk3399_cru.c stable/12/sys/arm64/rockchip/clk/rk3399_pmucru.c - copied unchanged from r341383, head/sys/arm64/rockchip/clk/rk3399_pmucru.c Modified: stable/12/sys/arm64/conf/GENERIC stable/12/sys/arm64/rockchip/clk/rk3328_cru.c stable/12/sys/arm64/rockchip/clk/rk_clk_armclk.c stable/12/sys/arm64/rockchip/clk/rk_clk_armclk.h stable/12/sys/arm64/rockchip/clk/rk_clk_composite.c stable/12/sys/arm64/rockchip/clk/rk_clk_composite.h stable/12/sys/arm64/rockchip/clk/rk_clk_pll.c stable/12/sys/arm64/rockchip/clk/rk_clk_pll.h stable/12/sys/arm64/rockchip/clk/rk_cru.c stable/12/sys/arm64/rockchip/clk/rk_cru.h stable/12/sys/arm64/rockchip/if_dwc_rk.c stable/12/sys/arm64/rockchip/rk805.c stable/12/sys/arm64/rockchip/rk805reg.h stable/12/sys/arm64/rockchip/rk_grf.c stable/12/sys/arm64/rockchip/rk_i2c.c stable/12/sys/arm64/rockchip/rk_pinctrl.c stable/12/sys/conf/files.arm64 stable/12/sys/conf/options.arm64 stable/12/sys/dev/mmc/host/dwmmc_rockchip.c Directory Properties: stable/12/ (props changed) Modified: stable/12/sys/arm64/conf/GENERIC ============================================================================== --- stable/12/sys/arm64/conf/GENERIC Wed Aug 7 18:16:28 2019 (r350686) +++ stable/12/sys/arm64/conf/GENERIC Wed Aug 7 18:26:32 2019 (r350687) @@ -95,6 +95,7 @@ options SOC_HISI_HI6220 options SOC_BRCM_BCM2837 options SOC_MARVELL_8K options SOC_ROCKCHIP_RK3328 +options SOC_ROCKCHIP_RK3399 options SOC_XILINX_ZYNQ # Timer drivers @@ -206,6 +207,8 @@ device fdt_pinctrl device gpioregulator device mv_gpio # Marvell GPIO controller device mvebu_pinctrl # Marvell Pinmux Controller +device rk_gpio # RockChip GPIO Controller +device rk_pinctrl # RockChip Pinmux Controller # I2C device aw_rsb # Allwinner Reduced Serial Bus Modified: stable/12/sys/arm64/rockchip/clk/rk3328_cru.c ============================================================================== --- stable/12/sys/arm64/rockchip/clk/rk3328_cru.c Wed Aug 7 18:16:28 2019 (r350686) +++ stable/12/sys/arm64/rockchip/clk/rk3328_cru.c Wed Aug 7 18:26:32 2019 (r350687) @@ -523,7 +523,7 @@ static struct rk_clk_pll_def apll = { .gate_offset = 0x200, .gate_shift = 0, .mode_reg = 0x80, - .mode_val = 0x1, + .mode_shift = 1, .flags = RK_CLK_PLL_HAVE_GATE, .frac_rates = rk3328_pll_frac_rates, }; @@ -539,7 +539,7 @@ static struct rk_clk_pll_def dpll = { .gate_offset = 0x200, .gate_shift = 1, .mode_reg = 0x80, - .mode_val = 0x8, + .mode_shift = 4, .flags = RK_CLK_PLL_HAVE_GATE, }; @@ -552,7 +552,7 @@ static struct rk_clk_pll_def cpll = { }, .base_offset = 0x40, .mode_reg = 0x80, - .mode_val = 0x80, + .mode_shift = 8, .rates = rk3328_pll_rates, }; @@ -567,7 +567,7 @@ static struct rk_clk_pll_def gpll = { .gate_offset = 0x200, .gate_shift = 2, .mode_reg = 0x80, - .mode_val = 0x800, + .mode_shift = 12, .flags = RK_CLK_PLL_HAVE_GATE, .frac_rates = rk3328_pll_frac_rates, }; @@ -583,7 +583,7 @@ static struct rk_clk_pll_def npll = { .gate_offset = 0x200, .gate_shift = 12, .mode_reg = 0x80, - .mode_val = 0x2, + .mode_shift = 1, .flags = RK_CLK_PLL_HAVE_GATE, .rates = rk3328_pll_rates, }; @@ -973,23 +973,23 @@ static struct rk_clk_composite_def i2c3 = { static struct rk_clk rk3328_clks[] = { { - .type = RK_CLK_PLL, + .type = RK3328_CLK_PLL, .clk.pll = &apll }, { - .type = RK_CLK_PLL, + .type = RK3328_CLK_PLL, .clk.pll = &dpll }, { - .type = RK_CLK_PLL, + .type = RK3328_CLK_PLL, .clk.pll = &cpll }, { - .type = RK_CLK_PLL, + .type = RK3328_CLK_PLL, .clk.pll = &gpll }, { - .type = RK_CLK_PLL, + .type = RK3328_CLK_PLL, .clk.pll = &npll }, Copied and modified: stable/12/sys/arm64/rockchip/clk/rk3399_cru.c (from r341383, head/sys/arm64/rockchip/clk/rk3399_cru.c) ============================================================================== --- head/sys/arm64/rockchip/clk/rk3399_cru.c Sat Dec 1 20:29:42 2018 (r341383, copy source) +++ stable/12/sys/arm64/rockchip/clk/rk3399_cru.c Wed Aug 7 18:26:32 2019 (r350687) @@ -61,6 +61,7 @@ __FBSDID("$FreeBSD$"); #define PCLK_I2C5 344 #define PCLK_I2C6 345 #define PCLK_I2C7 346 +#define HCLK_SDMMC 462 static struct rk_cru_gate rk3399_gates[] = { /* CRU_CLKGATE_CON0 */ @@ -99,6 +100,9 @@ static struct rk_cru_gate rk3399_gates[] = { CRU_GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_alive", 0x37c, 3) CRU_GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_alive", 0x37c, 4) CRU_GATE(PCLK_GPIO4, "pclk_gpio4", "pclk_alive", 0x37c, 5) + + /* CRU_CLKGATE_CON33 */ + CRU_GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_sd", 0x384, 8) }; @@ -1385,6 +1389,60 @@ static struct rk_clk_armclk_def armclk_b = { .nrates = nitems(rk3399_armclkb_rates), }; +/* + * sdmmc + */ + +#define HCLK_SD 461 + +static const char *hclk_sd_parents[] = {"cpll", "gpll"}; + +static struct rk_clk_composite_def hclk_sd = { + .clkdef = { + .id = HCLK_SD, + .name = "hclk_sd", + .parent_names = hclk_sd_parents, + .parent_cnt = nitems(hclk_sd_parents), + }, + + .muxdiv_offset = 0x134, + .mux_shift = 15, + .mux_width = 1, + + .div_shift = 8, + .div_width = 5, + + .gate_offset = 0x330, + .gate_shift = 13, + + .flags = RK_CLK_COMPOSITE_HAVE_MUX | RK_CLK_COMPOSITE_HAVE_GATE, +}; + +#define SCLK_SDMMC 76 + +static const char *sclk_sdmmc_parents[] = {"cpll", "gpll", "npll", "ppll"}; + +static struct rk_clk_composite_def sclk_sdmmc = { + .clkdef = { + .id = SCLK_SDMMC, + .name = "sclk_sdmmc", + .parent_names = sclk_sdmmc_parents, + .parent_cnt = nitems(sclk_sdmmc_parents), + }, + + .muxdiv_offset = 0x140, + .mux_shift = 8, + .mux_width = 3, + + .div_shift = 0, + .div_width = 7, + + .gate_offset = 0x318, + .gate_shift = 1, + + .flags = RK_CLK_COMPOSITE_HAVE_MUX | RK_CLK_COMPOSITE_HAVE_GATE, +}; + static struct rk_clk rk3399_clks[] = { { .type = RK3399_CLK_PLL, @@ -1483,6 +1541,15 @@ static struct rk_clk rk3399_clks[] = { { .type = RK_CLK_ARMCLK, .clk.armclk = &armclk_b, + }, + + { + .type = RK_CLK_COMPOSITE, + .clk.composite = &hclk_sd, + }, + { + .type = RK_CLK_COMPOSITE, + .clk.composite = &sclk_sdmmc, }, }; Copied: stable/12/sys/arm64/rockchip/clk/rk3399_pmucru.c (from r341383, head/sys/arm64/rockchip/clk/rk3399_pmucru.c) ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ stable/12/sys/arm64/rockchip/clk/rk3399_pmucru.c Wed Aug 7 18:26:32 2019 (r350687, copy of r341383, head/sys/arm64/rockchip/clk/rk3399_pmucru.c) @@ -0,0 +1,866 @@ +/*- + * SPDX-License-Identifier: BSD-2-Clause-FreeBSD + * + * Copyright (c) 2018 Emmanuel Vadot <manu@freebsd.org> + * Copyright (c) 2018 Greg V <greg@unrelenting.technology> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD$ + */ + +#include <sys/cdefs.h> +__FBSDID("$FreeBSD$"); + +#include <sys/param.h> +#include <sys/systm.h> +#include <sys/bus.h> +#include <sys/rman.h> +#include <sys/kernel.h> +#include <sys/module.h> +#include <machine/bus.h> + +#include <dev/fdt/simplebus.h> + +#include <dev/ofw/ofw_bus.h> +#include <dev/ofw/ofw_bus_subr.h> + +#include <dev/extres/clk/clk_div.h> +#include <dev/extres/clk/clk_fixed.h> +#include <dev/extres/clk/clk_mux.h> + +#include <arm64/rockchip/clk/rk_cru.h> + +/* GATES */ + +#define PCLK_PMU 20 +#define PCLK_GPIO0_PMU 23 +#define PCLK_GPIO1_PMU 24 +#define PCLK_I2C0_PMU 27 +#define PCLK_I2C4_PMU 28 +#define PCLK_I2C8_PMU 29 + +static struct rk_cru_gate rk3399_pmu_gates[] = { + /* PMUCRU_CLKGATE_CON1 */ + CRU_GATE(PCLK_PMU, "pclk_pmu", "pclk_pmu_src", 0x104, 0) + CRU_GATE(PCLK_GPIO0_PMU, "pclk_gpio0_pmu", "pclk_pmu_src", 0x104, 3) + CRU_GATE(PCLK_GPIO1_PMU, "pclk_gpio1_pmu", "pclk_pmu_src", 0x104, 4) + CRU_GATE(PCLK_I2C0_PMU, "pclk_i2c0_pmu", "pclk_pmu_src", 0x104, 7) + CRU_GATE(PCLK_I2C4_PMU, "pclk_i2c4_pmu", "pclk_pmu_src", 0x104, 8) + CRU_GATE(PCLK_I2C8_PMU, "pclk_i2c8_pmu", "pclk_pmu_src", 0x104, 9) +}; + + +/* + * PLLs + */ + +#define PLL_PPLL 1 + +static struct rk_clk_pll_rate rk3399_pll_rates[] = { + { + .freq = 2208000000, + .refdiv = 1, + .fbdiv = 92, + .postdiv1 = 1, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 2184000000, + .refdiv = 1, + .fbdiv = 91, + .postdiv1 = 1, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 2160000000, + .refdiv = 1, + .fbdiv = 90, + .postdiv1 = 1, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 2136000000, + .refdiv = 1, + .fbdiv = 89, + .postdiv1 = 1, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 2112000000, + .refdiv = 1, + .fbdiv = 88, + .postdiv1 = 1, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 2088000000, + .refdiv = 1, + .fbdiv = 87, + .postdiv1 = 1, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 2064000000, + .refdiv = 1, + .fbdiv = 86, + .postdiv1 = 1, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 2040000000, + .refdiv = 1, + .fbdiv = 85, + .postdiv1 = 1, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 2016000000, + .refdiv = 1, + .fbdiv = 84, + .postdiv1 = 1, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 1992000000, + .refdiv = 1, + .fbdiv = 83, + .postdiv1 = 1, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 1968000000, + .refdiv = 1, + .fbdiv = 82, + .postdiv1 = 1, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 1944000000, + .refdiv = 1, + .fbdiv = 81, + .postdiv1 = 1, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 1920000000, + .refdiv = 1, + .fbdiv = 80, + .postdiv1 = 1, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 1896000000, + .refdiv = 1, + .fbdiv = 79, + .postdiv1 = 1, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 1872000000, + .refdiv = 1, + .fbdiv = 78, + .postdiv1 = 1, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 1848000000, + .refdiv = 1, + .fbdiv = 77, + .postdiv1 = 1, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 1824000000, + .refdiv = 1, + .fbdiv = 76, + .postdiv1 = 1, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 1800000000, + .refdiv = 1, + .fbdiv = 75, + .postdiv1 = 1, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 1776000000, + .refdiv = 1, + .fbdiv = 74, + .postdiv1 = 1, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 1752000000, + .refdiv = 1, + .fbdiv = 73, + .postdiv1 = 1, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 1728000000, + .refdiv = 1, + .fbdiv = 72, + .postdiv1 = 1, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 1704000000, + .refdiv = 1, + .fbdiv = 71, + .postdiv1 = 1, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 1680000000, + .refdiv = 1, + .fbdiv = 70, + .postdiv1 = 1, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 1656000000, + .refdiv = 1, + .fbdiv = 69, + .postdiv1 = 1, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 1632000000, + .refdiv = 1, + .fbdiv = 68, + .postdiv1 = 1, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 1608000000, + .refdiv = 1, + .fbdiv = 67, + .postdiv1 = 1, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 1600000000, + .refdiv = 3, + .fbdiv = 200, + .postdiv1 = 1, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 1584000000, + .refdiv = 1, + .fbdiv = 66, + .postdiv1 = 1, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 1560000000, + .refdiv = 1, + .fbdiv = 65, + .postdiv1 = 1, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 1536000000, + .refdiv = 1, + .fbdiv = 64, + .postdiv1 = 1, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 1512000000, + .refdiv = 1, + .fbdiv = 63, + .postdiv1 = 1, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 1488000000, + .refdiv = 1, + .fbdiv = 62, + .postdiv1 = 1, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 1464000000, + .refdiv = 1, + .fbdiv = 61, + .postdiv1 = 1, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 1440000000, + .refdiv = 1, + .fbdiv = 60, + .postdiv1 = 1, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 1416000000, + .refdiv = 1, + .fbdiv = 59, + .postdiv1 = 1, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 1392000000, + .refdiv = 1, + .fbdiv = 58, + .postdiv1 = 1, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 1368000000, + .refdiv = 1, + .fbdiv = 57, + .postdiv1 = 1, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 1344000000, + .refdiv = 1, + .fbdiv = 56, + .postdiv1 = 1, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 1320000000, + .refdiv = 1, + .fbdiv = 55, + .postdiv1 = 1, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 1296000000, + .refdiv = 1, + .fbdiv = 54, + .postdiv1 = 1, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 1272000000, + .refdiv = 1, + .fbdiv = 53, + .postdiv1 = 1, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 1248000000, + .refdiv = 1, + .fbdiv = 52, + .postdiv1 = 1, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 1200000000, + .refdiv = 1, + .fbdiv = 50, + .postdiv1 = 1, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 1188000000, + .refdiv = 2, + .fbdiv = 99, + .postdiv1 = 1, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 1104000000, + .refdiv = 1, + .fbdiv = 46, + .postdiv1 = 1, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 1100000000, + .refdiv = 12, + .fbdiv = 550, + .postdiv1 = 1, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 1008000000, + .refdiv = 1, + .fbdiv = 84, + .postdiv1 = 2, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 1000000000, + .refdiv = 1, + .fbdiv = 125, + .postdiv1 = 3, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 984000000, + .refdiv = 1, + .fbdiv = 82, + .postdiv1 = 2, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 960000000, + .refdiv = 1, + .fbdiv = 80, + .postdiv1 = 2, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 936000000, + .refdiv = 1, + .fbdiv = 78, + .postdiv1 = 2, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 912000000, + .refdiv = 1, + .fbdiv = 76, + .postdiv1 = 2, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 900000000, + .refdiv = 4, + .fbdiv = 300, + .postdiv1 = 2, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 888000000, + .refdiv = 1, + .fbdiv = 74, + .postdiv1 = 2, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 864000000, + .refdiv = 1, + .fbdiv = 72, + .postdiv1 = 2, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 840000000, + .refdiv = 1, + .fbdiv = 70, + .postdiv1 = 2, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 816000000, + .refdiv = 1, + .fbdiv = 68, + .postdiv1 = 2, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 800000000, + .refdiv = 1, + .fbdiv = 100, + .postdiv1 = 3, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 700000000, + .refdiv = 6, + .fbdiv = 350, + .postdiv1 = 2, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 696000000, + .refdiv = 1, + .fbdiv = 58, + .postdiv1 = 2, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 676000000, + .refdiv = 3, + .fbdiv = 169, + .postdiv1 = 2, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 600000000, + .refdiv = 1, + .fbdiv = 75, + .postdiv1 = 3, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 594000000, + .refdiv = 1, + .fbdiv = 99, + .postdiv1 = 4, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 533250000, + .refdiv = 8, + .fbdiv = 711, + .postdiv1 = 4, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 504000000, + .refdiv = 1, + .fbdiv = 63, + .postdiv1 = 3, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 500000000, + .refdiv = 6, + .fbdiv = 250, + .postdiv1 = 2, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 408000000, + .refdiv = 1, + .fbdiv = 68, + .postdiv1 = 2, + .postdiv2 = 2, + .dsmpd = 1, + }, + { + .freq = 312000000, + .refdiv = 1, + .fbdiv = 52, + .postdiv1 = 2, + .postdiv2 = 2, + .dsmpd = 1, + }, + { + .freq = 297000000, + .refdiv = 1, + .fbdiv = 99, + .postdiv1 = 4, + .postdiv2 = 2, + .dsmpd = 1, + }, + { + .freq = 216000000, + .refdiv = 1, + .fbdiv = 72, + .postdiv1 = 4, + .postdiv2 = 2, + .dsmpd = 1, + }, + { + .freq = 148500000, + .refdiv = 1, + .fbdiv = 99, + .postdiv1 = 4, + .postdiv2 = 4, + .dsmpd = 1, + }, + { + .freq = 106500000, + .refdiv = 1, + .fbdiv = 71, + .postdiv1 = 4, + .postdiv2 = 4, + .dsmpd = 1, + }, + { + .freq = 96000000, + .refdiv = 1, + .fbdiv = 64, + .postdiv1 = 4, + .postdiv2 = 4, + .dsmpd = 1, + }, + { + .freq = 74250000, + .refdiv = 2, + .fbdiv = 99, + .postdiv1 = 4, + .postdiv2 = 4, + .dsmpd = 1, + }, + { + .freq = 65000000, + .refdiv = 1, + .fbdiv = 65, + .postdiv1 = 6, + .postdiv2 = 4, + .dsmpd = 1, + }, + { + .freq = 54000000, + .refdiv = 1, + .fbdiv = 54, + .postdiv1 = 6, + .postdiv2 = 4, + .dsmpd = 1, + }, + { + .freq = 27000000, + .refdiv = 1, + .fbdiv = 27, + .postdiv1 = 6, + .postdiv2 = 4, + .dsmpd = 1, + }, + {}, +}; + +static const char *pll_parents[] = {"xin24m"}; + +static struct rk_clk_pll_def ppll = { + .clkdef = { + .id = PLL_PPLL, + .name = "ppll", + .parent_names = pll_parents, + .parent_cnt = nitems(pll_parents), + }, + .base_offset = 0x00, + + .rates = rk3399_pll_rates, +}; + +static const char *pmu_parents[] = {"ppll"}; + +#define PCLK_PMU_SRC 19 + +static struct rk_clk_composite_def pclk_pmu_src = { + .clkdef = { + .id = PCLK_PMU_SRC, + .name = "pclk_pmu_src", + .parent_names = pmu_parents, + .parent_cnt = nitems(pmu_parents), + }, + /* PMUCRU_CLKSEL_CON0 */ + .muxdiv_offset = 0x80, + + .div_shift = 0, + .div_width = 5, +}; + + +#define SCLK_I2C0_PMU 9 +#define SCLK_I2C4_PMU 10 +#define SCLK_I2C8_PMU 11 + +static struct rk_clk_composite_def i2c0 = { + .clkdef = { + .id = SCLK_I2C0_PMU, + .name = "clk_i2c0_pmu", + .parent_names = pmu_parents, + .parent_cnt = nitems(pmu_parents), + }, + /* PMUCRU_CLKSEL_CON2 */ + .muxdiv_offset = 0x88, + + .div_shift = 0, + .div_width = 7, + + /* PMUCRU_CLKGATE_CON0 */ + .gate_offset = 0x100, + .gate_shift = 9, + + .flags = RK_CLK_COMPOSITE_HAVE_GATE, +}; + +static struct rk_clk_composite_def i2c8 = { + .clkdef = { + .id = SCLK_I2C8_PMU, + .name = "clk_i2c8_pmu", + .parent_names = pmu_parents, + .parent_cnt = nitems(pmu_parents), + }, + /* PMUCRU_CLKSEL_CON2 */ + .muxdiv_offset = 0x88, + + .div_shift = 8, + .div_width = 7, + + /* PMUCRU_CLKGATE_CON0 */ + .gate_offset = 0x100, + .gate_shift = 11, + + .flags = RK_CLK_COMPOSITE_HAVE_GATE, +}; + +static struct rk_clk_composite_def i2c4 = { + .clkdef = { + .id = SCLK_I2C4_PMU, + .name = "clk_i2c4_pmu", + .parent_names = pmu_parents, + .parent_cnt = nitems(pmu_parents), + }, + /* PMUCRU_CLKSEL_CON3 */ + .muxdiv_offset = 0x8c, + + .div_shift = 0, + .div_width = 7, + + /* PMUCRU_CLKGATE_CON0 */ + .gate_offset = 0x100, + .gate_shift = 10, + + .flags = RK_CLK_COMPOSITE_HAVE_GATE, +}; + +static struct rk_clk rk3399_pmu_clks[] = { + { + .type = RK3399_CLK_PLL, + .clk.pll = &ppll + }, + + { + .type = RK_CLK_COMPOSITE, + .clk.composite = &pclk_pmu_src + }, *** DIFF OUTPUT TRUNCATED AT 1000 LINES ***
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