Date: Wed, 12 Nov 1997 17:47:08 +1100 From: Bruce Evans <bde@zeta.org.au> To: bde@zeta.org.au, mouth@ibm.net Cc: hackers@freebsd.org Subject: Re: Status of 650 UART support Message-ID: <199711120647.RAA10782@godzilla.zeta.org.au>
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>>RTS flow control is almost useless for preventing this error, since >> the interrupt handler must run to invoke RTS flow control. > >Did you know that the 650 UART has on-chip "auto" RTS flow control >which can be invoked by the chip itself when the UART FIFO trigger >level is reached? That's why I want to use my 650 UARTs in 650 mode >rather than 550 compatibility mode. Yes. I'm not sure if it actually works (I don't have any 16650s). On some (early? all?) 16650s it is said to be just a pessimization to use it, since it is invoked when the trigger level is reached, so it is invoked for almost every input interrupt. I don't know what happens when the driver sets RTS directly. Perhaps auto flow control interferes with this and causes your buffer overflows. Possible fix: turn off auto flow control at least when clearing RTS directly. >>The gap between the high water mark and the end of the fifo (256 - 192) >>needs to be larger than the hardware fifo size. I think it is for >>the 16550, so the 16550 bug must be elsewhere. > >You mean 650? 16650 :-). >A Startech 16C650 has a 32 byte FIFO buffer while the quad 16C654, >four UARTs on a chip, each have 64 bytes. A 64-byte fifo probably won't work unless the fifo trigger level is reduced (defeating the point of the larger fifo). There may be just enough margin if the default (highest) trigger level is enough below 64. I think the best available setup is to use 16550 mode with the tx fifo size set to match the flow control. The 16650 configuration is too specific - it forces 16650 flow control and a 32 byte tx fifo size. The interrupt latency is low enough for auto flow control to be unnecessary in most cases (and there is another 6 character times of slop available by reducing the 16550 trigger level from 14 to 8 to handle overloaded cases). Another problem with auto flow control is that it doesn't actually work if the sender can't stop soon enough. E.g., if the sender is a 16550, then it can't reasonably stop before sending 16 characters if it has 16 characters in its tx fifo. The receiver must have a rx fifo trigger level 16+ below the fifo size to handle this completely in hardware (+ = a few more to give the interrupt handler time to run before flow control is actually invoked). 16+ below the 16650 fifo size of 32 is too many. 16+ below the 16654 fifo size of 64 is better. >I increased the software buffer size from 256 to 512, and that seemed >to reduce the number of overflows, but a burst of disk activity would >still trigger one even with the larger buffer. That breaks the watermarks in the tty buffer unless the tty buffer size (TTYHOG) is increased too. Bruce
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