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From: Alexander Kabaev <kan@FreeBSD.org>
Date: Fri, 6 Jan 2017 00:07:36 +0000 (UTC)
To: src-committers@freebsd.org, svn-src-all@freebsd.org,
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Subject: svn commit: r311463 - head/sys/mips/ingenic
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Author: kan
Date: Fri Jan  6 00:07:36 2017
New Revision: 311463
URL: https://svnweb.freebsd.org/changeset/base/311463

Log:
  Remove redundant cache initialization in JZ4780 SMP startup code
  
  This was done out of pure paranoia when hunting for bugs in cache
  and is not really required.

Modified:
  head/sys/mips/ingenic/jz4780_mpboot.S

Modified: head/sys/mips/ingenic/jz4780_mpboot.S
==============================================================================
--- head/sys/mips/ingenic/jz4780_mpboot.S	Thu Jan  5 21:28:25 2017	(r311462)
+++ head/sys/mips/ingenic/jz4780_mpboot.S	Fri Jan  6 00:07:36 2017	(r311463)
@@ -27,36 +27,19 @@
  */
 
 #include <machine/asm.h>
-#include <machine/cpu.h>
-#include <machine/cpuregs.h>
-#include <machine/cache_r4k.h>
-
 #include "assym.s"
 
-#define CACHE_SIZE (32 * 1024)
-#define CACHE_LINESIZE 32
-
 	.text
 	.set	noat
 	.set	noreorder
 	.section .text.mpentry_jz4780
 	.balign 0x10000
 
+/*
+ * JZ4870 has stricter alignment requirement for
+ * CPU entry point. Enforce it in CPU-specific
+ * file.
+ */
 GLOBAL(jz4780_mpentry)
-
-	/* Initialize caches */
-	li	t0, MIPS_KSEG0_START
-	ori	t1, t0, CACHE_SIZE
-	mtc0	zero, MIPS_COP_0_TAG_LO
-	COP0_SYNC
-1:	cache	CACHEOP_R4K_INDEX_STORE_TAG | CACHE_R4K_I, 0(t0)
-	cache	CACHEOP_R4K_INDEX_STORE_TAG | CACHE_R4K_D, 0(t0)
-	bne	t0, t1, 1b
-	addiu	t0, t0, CACHE_LINESIZE
-
-	/* Set TLB page mask */
-	mtc0	zero, MIPS_COP_0_TLB_PG_MASK
-	COP0_SYNC
-
 	j	mpentry
 	nop