Date: Thu, 8 Mar 2007 11:50:32 GMT From: Paolo Pisati <piso@FreeBSD.org> To: Perforce Change Reviews <perforce@freebsd.org> Subject: PERFORCE change 115518 for review Message-ID: <200703081150.l28BoWLV095977@repoman.freebsd.org>
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http://perforce.freebsd.org/chv.cgi?CH=115518 Change 115518 by piso@piso_newluxor on 2007/03/08 11:49:43 IFC@115517 Affected files ... .. //depot/projects/soc2006/intr_filter/amd64/amd64/busdma_machdep.c#3 integrate .. //depot/projects/soc2006/intr_filter/amd64/amd64/intr_machdep.c#24 integrate .. //depot/projects/soc2006/intr_filter/amd64/amd64/local_apic.c#8 integrate .. //depot/projects/soc2006/intr_filter/amd64/amd64/mp_machdep.c#7 integrate .. //depot/projects/soc2006/intr_filter/amd64/include/intr_machdep.h#8 integrate .. //depot/projects/soc2006/intr_filter/amd64/include/smp.h#2 integrate .. //depot/projects/soc2006/intr_filter/conf/files.sparc64#6 integrate .. //depot/projects/soc2006/intr_filter/dev/bge/if_bge.c#13 integrate .. //depot/projects/soc2006/intr_filter/dev/fb/creator.c#4 integrate .. //depot/projects/soc2006/intr_filter/dev/sound/pci/ds1.c#3 integrate .. //depot/projects/soc2006/intr_filter/dev/sound/pci/emu10k1.c#5 integrate .. //depot/projects/soc2006/intr_filter/dev/sound/pci/emu10kx-pcm.c#4 integrate .. //depot/projects/soc2006/intr_filter/dev/zs/z8530reg.h#2 delete .. //depot/projects/soc2006/intr_filter/dev/zs/z8530var.h#6 delete .. //depot/projects/soc2006/intr_filter/dev/zs/zs.c#7 delete .. //depot/projects/soc2006/intr_filter/dev/zs/zs_macio.c#6 delete .. //depot/projects/soc2006/intr_filter/i386/i386/busdma_machdep.c#3 integrate .. //depot/projects/soc2006/intr_filter/i386/i386/intr_machdep.c#31 integrate .. //depot/projects/soc2006/intr_filter/i386/i386/local_apic.c#8 integrate .. //depot/projects/soc2006/intr_filter/i386/i386/mp_machdep.c#7 integrate .. //depot/projects/soc2006/intr_filter/i386/include/intr_machdep.h#8 integrate .. //depot/projects/soc2006/intr_filter/i386/include/smp.h#2 integrate .. //depot/projects/soc2006/intr_filter/ia64/ia64/busdma_machdep.c#3 integrate .. //depot/projects/soc2006/intr_filter/kern/kern_clock.c#6 integrate .. //depot/projects/soc2006/intr_filter/kern/kern_jail.c#7 integrate .. //depot/projects/soc2006/intr_filter/kern/kern_kse.c#5 integrate .. //depot/projects/soc2006/intr_filter/kern/kern_rwlock.c#6 integrate .. //depot/projects/soc2006/intr_filter/kern/kern_synch.c#9 integrate .. //depot/projects/soc2006/intr_filter/kern/sched_core.c#6 integrate .. //depot/projects/soc2006/intr_filter/kern/sched_ule.c#11 integrate .. //depot/projects/soc2006/intr_filter/kern/subr_prf.c#6 integrate .. //depot/projects/soc2006/intr_filter/kern/subr_smp.c#2 integrate .. //depot/projects/soc2006/intr_filter/kern/vfs_bio.c#9 integrate .. //depot/projects/soc2006/intr_filter/net/ethernet.h#4 integrate .. //depot/projects/soc2006/intr_filter/net80211/_ieee80211.h#5 integrate .. //depot/projects/soc2006/intr_filter/net80211/ieee80211_freebsd.h#4 integrate .. //depot/projects/soc2006/intr_filter/net80211/ieee80211_input.c#9 integrate .. //depot/projects/soc2006/intr_filter/net80211/ieee80211_node.c#5 integrate .. //depot/projects/soc2006/intr_filter/net80211/ieee80211_proto.c#5 integrate .. //depot/projects/soc2006/intr_filter/net80211/ieee80211_proto.h#4 integrate .. //depot/projects/soc2006/intr_filter/netinet/tcp_input.c#10 integrate .. //depot/projects/soc2006/intr_filter/powerpc/powerpc/nexus.c#3 integrate .. //depot/projects/soc2006/intr_filter/powerpc/powerpc/pic_if.m#3 integrate .. //depot/projects/soc2006/intr_filter/sparc64/central/central.c#2 integrate .. //depot/projects/soc2006/intr_filter/sparc64/fhc/fhc.c#8 integrate .. //depot/projects/soc2006/intr_filter/sparc64/fhc/fhc_central.c#2 delete .. //depot/projects/soc2006/intr_filter/sparc64/fhc/fhc_nexus.c#2 delete .. //depot/projects/soc2006/intr_filter/sparc64/fhc/fhcvar.h#2 delete .. //depot/projects/soc2006/intr_filter/sparc64/include/bus_private.h#2 integrate .. //depot/projects/soc2006/intr_filter/sparc64/include/iommureg.h#2 integrate .. //depot/projects/soc2006/intr_filter/sparc64/include/nexusvar.h#2 delete .. //depot/projects/soc2006/intr_filter/sparc64/include/ofw_nexus.h#3 integrate .. //depot/projects/soc2006/intr_filter/sparc64/include/ofw_upa.h#2 delete .. //depot/projects/soc2006/intr_filter/sparc64/pci/psycho.c#14 integrate .. //depot/projects/soc2006/intr_filter/sparc64/pci/psychovar.h#2 integrate .. //depot/projects/soc2006/intr_filter/sparc64/sbus/sbus.c#12 integrate .. //depot/projects/soc2006/intr_filter/sparc64/sparc64/bus_machdep.c#3 integrate .. //depot/projects/soc2006/intr_filter/sparc64/sparc64/iommu.c#2 integrate .. //depot/projects/soc2006/intr_filter/sparc64/sparc64/nexus.c#4 integrate .. //depot/projects/soc2006/intr_filter/sparc64/sparc64/sc_machdep.c#2 integrate .. //depot/projects/soc2006/intr_filter/sys/buf.h#4 integrate .. //depot/projects/soc2006/intr_filter/sys/mutex.h#7 integrate .. //depot/projects/soc2006/intr_filter/sys/proc.h#8 integrate .. //depot/projects/soc2006/intr_filter/sys/rwlock.h#6 integrate Differences ... ==== //depot/projects/soc2006/intr_filter/amd64/amd64/busdma_machdep.c#3 (text+ko) ==== @@ -25,7 +25,7 @@ */ #include <sys/cdefs.h> -__FBSDID("$FreeBSD: src/sys/amd64/amd64/busdma_machdep.c,v 1.78 2006/10/15 16:52:59 hrs Exp $"); +__FBSDID("$FreeBSD: src/sys/amd64/amd64/busdma_machdep.c,v 1.79 2007/03/06 18:28:42 scottl Exp $"); #include <sys/param.h> #include <sys/systm.h> @@ -906,7 +906,6 @@ * want to add support for invalidating * the caches on broken hardware */ - dmat->bounce_zone->total_bounced++; CTR4(KTR_BUSDMA, "%s: tag %p tag flags 0x%x op 0x%x " "performing bounce", __func__, op, dmat, dmat->flags); @@ -917,6 +916,7 @@ bpage->datacount); bpage = STAILQ_NEXT(bpage, links); } + dmat->bounce_zone->total_bounced++; } if (op & BUS_DMASYNC_POSTREAD) { @@ -926,6 +926,7 @@ bpage->datacount); bpage = STAILQ_NEXT(bpage, links); } + dmat->bounce_zone->total_bounced++; } } } ==== //depot/projects/soc2006/intr_filter/amd64/amd64/intr_machdep.c#24 (text+ko) ==== @@ -26,7 +26,7 @@ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * - * $FreeBSD: src/sys/amd64/amd64/intr_machdep.c,v 1.29 2007/02/23 20:03:23 jhb Exp $ + * $FreeBSD: src/sys/amd64/amd64/intr_machdep.c,v 1.30 2007/03/06 17:16:46 jhb Exp $ */ /* @@ -53,6 +53,7 @@ #include <sys/systm.h> #include <machine/clock.h> #include <machine/intr_machdep.h> +#include <machine/smp.h> #ifdef DDB #include <ddb/ddb.h> #endif @@ -449,8 +450,9 @@ * allocate CPUs round-robin. */ -static u_int cpu_apic_ids[MAXCPU]; -static int current_cpu, num_cpus; +/* The BSP is always a valid target. */ +static cpumask_t intr_cpus = (1 << 0); +static int current_cpu, num_cpus = 1; static void intr_assign_next_cpu(struct intsrc *isrc) @@ -463,25 +465,29 @@ */ pic = isrc->is_pic; apic_id = cpu_apic_ids[current_cpu]; - current_cpu++; - if (current_cpu >= num_cpus) - current_cpu = 0; pic->pic_assign_cpu(isrc, apic_id); + do { + current_cpu++; + if (current_cpu >= num_cpus) + current_cpu = 0; + } while (!(intr_cpus & (1 << current_cpu))); } /* - * Add a local APIC ID to our list of valid local APIC IDs that can - * be destinations of interrupts. + * Add a CPU to our mask of valid CPUs that can be destinations of + * interrupts. */ void -intr_add_cpu(u_int apic_id) +intr_add_cpu(u_int cpu) { + if (cpu >= MAXCPU) + panic("%s: Invalid CPU ID", __func__); if (bootverbose) - printf("INTR: Adding local APIC %d as a target\n", apic_id); - if (num_cpus >= MAXCPU) - panic("WARNING: Local APIC IDs exhausted!"); - cpu_apic_ids[num_cpus] = apic_id; + printf("INTR: Adding local APIC %d as a target\n", + cpu_apic_ids[cpu]); + + intr_cpus |= (1 << cpu); num_cpus++; } ==== //depot/projects/soc2006/intr_filter/amd64/amd64/local_apic.c#8 (text+ko) ==== @@ -32,7 +32,7 @@ */ #include <sys/cdefs.h> -__FBSDID("$FreeBSD: src/sys/amd64/amd64/local_apic.c,v 1.35 2007/03/05 20:35:16 jhb Exp $"); +__FBSDID("$FreeBSD: src/sys/amd64/amd64/local_apic.c,v 1.36 2007/03/06 17:16:46 jhb Exp $"); #include "opt_hwpmc_hooks.h" @@ -220,7 +220,6 @@ /* Set BSP's per-CPU local APIC ID. */ PCPU_SET(apic_id, lapic_id()); - intr_add_cpu(PCPU_GET(apic_id)); /* Local APIC timer interrupt. */ setidt(APIC_TIMER_INT, IDTVEC(timerint), SDT_SYSIGT, SEL_KPL, 0); ==== //depot/projects/soc2006/intr_filter/amd64/amd64/mp_machdep.c#7 (text+ko) ==== @@ -25,7 +25,7 @@ */ #include <sys/cdefs.h> -__FBSDID("$FreeBSD: src/sys/amd64/amd64/mp_machdep.c,v 1.282 2007/03/05 21:40:10 alc Exp $"); +__FBSDID("$FreeBSD: src/sys/amd64/amd64/mp_machdep.c,v 1.283 2007/03/06 17:16:46 jhb Exp $"); #include "opt_cpu.h" #include "opt_kstack_pages.h" @@ -152,7 +152,7 @@ int cpu_bsp:1; int cpu_disabled:1; } static cpu_info[MAXCPU]; -static int cpu_apic_ids[MAXCPU]; +int cpu_apic_ids[MAXCPU]; /* Holds pending bitmap based IPIs per CPU */ static volatile u_int cpu_ipi_pending[MAXCPU]; @@ -625,10 +625,11 @@ static void set_interrupt_apic_ids(void) { - u_int apic_id; + u_int i, apic_id; - for (apic_id = 0; apic_id < MAXCPU; apic_id++) { - if (!cpu_info[apic_id].cpu_present) + for (i = 0; i < MAXCPU; i++) { + apic_id = cpu_apic_ids[i]; + if (apic_id == -1) continue; if (cpu_info[apic_id].cpu_bsp) continue; @@ -640,7 +641,7 @@ apic_id % hyperthreading_cpus != 0) continue; - intr_add_cpu(apic_id); + intr_add_cpu(i); } } ==== //depot/projects/soc2006/intr_filter/amd64/include/intr_machdep.h#8 (text+ko) ==== @@ -23,7 +23,7 @@ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * - * $FreeBSD: src/sys/amd64/include/intr_machdep.h,v 1.15 2007/02/23 12:18:26 piso Exp $ + * $FreeBSD: src/sys/amd64/include/intr_machdep.h,v 1.16 2007/03/06 17:16:46 jhb Exp $ */ #ifndef __MACHINE_INTR_MACHDEP_H__ @@ -131,9 +131,7 @@ void elcr_resume(void); void elcr_write_trigger(u_int irq, enum intr_trigger trigger); #ifdef SMP -void intr_add_cpu(u_int apic_id); -#else -#define intr_add_cpu(apic_id) +void intr_add_cpu(u_int cpu); #endif int intr_add_handler(const char *name, int vector, driver_filter_t filter, driver_intr_t handler, void *arg, enum intr_type flags, ==== //depot/projects/soc2006/intr_filter/amd64/include/smp.h#2 (text+ko) ==== @@ -6,7 +6,7 @@ * this stuff is worth it, you can buy me a beer in return. Poul-Henning Kamp * ---------------------------------------------------------------------------- * - * $FreeBSD: src/sys/amd64/include/smp.h,v 1.88 2006/05/01 21:36:47 jhb Exp $ + * $FreeBSD: src/sys/amd64/include/smp.h,v 1.89 2007/03/06 17:16:46 jhb Exp $ * */ @@ -34,6 +34,7 @@ extern int boot_cpu_id; extern struct pcb stoppcbs[]; extern struct mtx smp_tlb_mtx; +extern int cpu_apic_ids[]; /* IPI handlers */ inthand_t ==== //depot/projects/soc2006/intr_filter/conf/files.sparc64#6 (text+ko) ==== @@ -1,7 +1,7 @@ # This file tells config what files go into building a kernel, # files marked standard are always included. # -# $FreeBSD: src/sys/conf/files.sparc64,v 1.87 2007/01/20 12:53:30 marius Exp $ +# $FreeBSD: src/sys/conf/files.sparc64,v 1.88 2007/03/07 21:13:49 marius Exp $ # # The long compile-with and dependency lines are required because of # limitations in config: backslash-newline doesn't work in strings, and @@ -80,8 +80,6 @@ sparc64/ebus/ebus.c optional ebus sparc64/fhc/clkbrd.c optional clkbrd fhc sparc64/fhc/fhc.c optional fhc -sparc64/fhc/fhc_central.c optional fhc central -sparc64/fhc/fhc_nexus.c optional fhc sparc64/isa/isa.c optional isa sparc64/isa/isa_dma.c optional isa sparc64/isa/ofw_isa.c optional ebus | isa ==== //depot/projects/soc2006/intr_filter/dev/bge/if_bge.c#13 (text+ko) ==== @@ -32,7 +32,7 @@ */ #include <sys/cdefs.h> -__FBSDID("$FreeBSD: src/sys/dev/bge/if_bge.c,v 1.179 2007/02/23 12:18:34 piso Exp $"); +__FBSDID("$FreeBSD: src/sys/dev/bge/if_bge.c,v 1.183 2007/03/08 00:49:26 jkim Exp $"); /* * Broadcom BCM570x family gigabit ethernet driver for FreeBSD. @@ -521,7 +521,7 @@ /* Reset the EEPROM, load the clock period. */ CSR_WRITE_4(sc, BGE_EE_ADDR, - BGE_EEADDR_RESET|BGE_EEHALFCLK(BGE_HALFCLK_384SCL)); + BGE_EEADDR_RESET | BGE_EEHALFCLK(BGE_HALFCLK_384SCL)); DELAY(20); /* Issue the read EEPROM command. */ @@ -594,8 +594,8 @@ DELAY(40); } - CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ|BGE_MICOMM_BUSY| - BGE_MIPHY(phy)|BGE_MIREG(reg)); + CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ | BGE_MICOMM_BUSY | + BGE_MIPHY(phy) | BGE_MIREG(reg)); for (i = 0; i < BGE_TIMEOUT; i++) { val = CSR_READ_4(sc, BGE_MI_COMM); @@ -639,8 +639,8 @@ DELAY(40); } - CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE|BGE_MICOMM_BUSY| - BGE_MIPHY(phy)|BGE_MIREG(reg)|val); + CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE | BGE_MICOMM_BUSY | + BGE_MIPHY(phy) | BGE_MIREG(reg) | val); for (i = 0; i < BGE_TIMEOUT; i++) { if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY)) @@ -778,7 +778,7 @@ * Fill in the extended RX buffer descriptor. */ r = &sc->bge_ldata.bge_rx_jumbo_ring[i]; - r->bge_flags = BGE_RXBDFLAG_JUMBO_RING|BGE_RXBDFLAG_END; + r->bge_flags = BGE_RXBDFLAG_JUMBO_RING | BGE_RXBDFLAG_END; r->bge_idx = i; r->bge_len3 = r->bge_len2 = r->bge_len1 = 0; switch (nsegs) { @@ -828,7 +828,7 @@ bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag, sc->bge_cdata.bge_rx_std_ring_map, - BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); + BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); sc->bge_std = i - 1; CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); @@ -869,7 +869,7 @@ bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag, sc->bge_cdata.bge_rx_jumbo_ring_map, - BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); + BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); sc->bge_jumbo = i - 1; @@ -1070,7 +1070,7 @@ if (sc->bge_asf_mode) { bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM_FW, BGE_FW_PAUSE); CSR_WRITE_4(sc, BGE_CPU_EVENT, - CSR_READ_4(sc, BGE_CPU_EVENT) != (1 << 14)); + CSR_READ_4(sc, BGE_CPU_EVENT) | (1 << 14)); for (i = 0; i < 100; i++ ) { if (!(CSR_READ_4(sc, BGE_CPU_EVENT) & (1 << 14))) @@ -1121,19 +1121,19 @@ if (sc->bge_flags & BGE_FLAG_PCIE) { /* PCI Express bus */ dma_rw_ctl = BGE_PCI_READ_CMD | BGE_PCI_WRITE_CMD | - BGE_PCIDMARWCTL_RD_WAT_SHIFT(0xf) | + BGE_PCIDMARWCTL_RD_WAT_SHIFT(0xF) | BGE_PCIDMARWCTL_WR_WAT_SHIFT(0x2); } else if (sc->bge_flags & BGE_FLAG_PCIX) { /* PCI-X bus */ if (BGE_IS_5714_FAMILY(sc)) { - dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD; + dma_rw_ctl = BGE_PCI_READ_CMD | BGE_PCI_WRITE_CMD; dma_rw_ctl &= ~BGE_PCIDMARWCTL_ONEDMA_ATONCE; /* XXX */ /* XXX magic values, Broadcom-supplied Linux driver */ + dma_rw_ctl |= (1 << 20) | (1 << 18); if (sc->bge_asicrev == BGE_ASICREV_BCM5780) - dma_rw_ctl |= (1 << 20) | (1 << 18) | - BGE_PCIDMARWCTL_ONEDMA_ATONCE; + dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE; else - dma_rw_ctl |= (1 << 20) | (1 << 18) | (1 << 15); + dma_rw_ctl |= 1 << 15; } else if (sc->bge_asicrev == BGE_ASICREV_BCM5704) /* @@ -1147,7 +1147,7 @@ dma_rw_ctl = BGE_PCI_READ_CMD | BGE_PCI_WRITE_CMD | BGE_PCIDMARWCTL_RD_WAT_SHIFT(0x3) | BGE_PCIDMARWCTL_WR_WAT_SHIFT(0x3) | - 0x0f; + 0x0F; /* * 5703 and 5704 need ONEDMA_AT_ONCE as a workaround @@ -1157,7 +1157,7 @@ sc->bge_asicrev == BGE_ASICREV_BCM5704) { uint32_t tmp; - tmp = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1f; + tmp = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1F; if (tmp == 0x6 || tmp == 0x7) dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE; } @@ -1166,7 +1166,7 @@ dma_rw_ctl = BGE_PCI_READ_CMD | BGE_PCI_WRITE_CMD | BGE_PCIDMARWCTL_RD_WAT_SHIFT(0x7) | BGE_PCIDMARWCTL_WR_WAT_SHIFT(0x7) | - 0x0f; + 0x0F; if (sc->bge_asicrev == BGE_ASICREV_BCM5703 || sc->bge_asicrev == BGE_ASICREV_BCM5704 || @@ -1177,8 +1177,8 @@ /* * Set up general mode register. */ - CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS| - BGE_MODECTL_MAC_ATTN_INTR|BGE_MODECTL_HOST_SEND_BDS| + CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS | + BGE_MODECTL_MAC_ATTN_INTR | BGE_MODECTL_HOST_SEND_BDS | BGE_MODECTL_TX_NO_PHDR_CSUM); /* @@ -1205,7 +1205,7 @@ #endif /* Set the timer prescaler (always 66Mhz) */ - CSR_WRITE_4(sc, BGE_MISC_CFG, 65 << 1/*BGE_32BITTIME_66MHZ*/); + CSR_WRITE_4(sc, BGE_MISC_CFG, BGE_32BITTIME_66MHZ); return (0); } @@ -1260,7 +1260,7 @@ /* Enable buffer manager */ if (!(BGE_IS_5705_PLUS(sc))) { CSR_WRITE_4(sc, BGE_BMAN_MODE, - BGE_BMANMODE_ENABLE|BGE_BMANMODE_LOMBUF_ATTN); + BGE_BMANMODE_ENABLE | BGE_BMANMODE_LOMBUF_ATTN); /* Poll for buffer manager start indication */ for (i = 0; i < BGE_TIMEOUT; i++) { @@ -1330,7 +1330,7 @@ sc->bge_cdata.bge_rx_jumbo_ring_map, BUS_DMASYNC_PREREAD); rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0, - BGE_RCB_FLAG_USE_EXT_RX_BD|BGE_RCB_FLAG_RING_DISABLED); + BGE_RCB_FLAG_USE_EXT_RX_BD | BGE_RCB_FLAG_RING_DISABLED); rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS; CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi); @@ -1500,7 +1500,7 @@ /* Turn on RX BD completion state machine and enable attentions */ CSR_WRITE_4(sc, BGE_RBDC_MODE, - BGE_RBDCMODE_ENABLE|BGE_RBDCMODE_ATTN); + BGE_RBDCMODE_ENABLE | BGE_RBDCMODE_ATTN); /* Turn on RX list placement state machine */ CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); @@ -1510,10 +1510,10 @@ CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); /* Turn on DMA, clear stats */ - CSR_WRITE_4(sc, BGE_MAC_MODE, BGE_MACMODE_TXDMA_ENB| - BGE_MACMODE_RXDMA_ENB|BGE_MACMODE_RX_STATS_CLEAR| - BGE_MACMODE_TX_STATS_CLEAR|BGE_MACMODE_RX_STATS_ENB| - BGE_MACMODE_TX_STATS_ENB|BGE_MACMODE_FRMHDR_DMA_ENB| + CSR_WRITE_4(sc, BGE_MAC_MODE, BGE_MACMODE_TXDMA_ENB | + BGE_MACMODE_RXDMA_ENB | BGE_MACMODE_RX_STATS_CLEAR | + BGE_MACMODE_TX_STATS_CLEAR | BGE_MACMODE_RX_STATS_ENB | + BGE_MACMODE_TX_STATS_ENB | BGE_MACMODE_FRMHDR_DMA_ENB | ((sc->bge_flags & BGE_FLAG_TBI) ? BGE_PORTMODE_TBI : BGE_PORTMODE_MII)); @@ -1522,29 +1522,29 @@ #ifdef notdef /* Assert GPIO pins for PHY reset */ - BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0| - BGE_MLC_MISCIO_OUT1|BGE_MLC_MISCIO_OUT2); - BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0| - BGE_MLC_MISCIO_OUTEN1|BGE_MLC_MISCIO_OUTEN2); + BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0 | + BGE_MLC_MISCIO_OUT1 | BGE_MLC_MISCIO_OUT2); + BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0 | + BGE_MLC_MISCIO_OUTEN1 | BGE_MLC_MISCIO_OUTEN2); #endif /* Turn on DMA completion state machine */ if (!(BGE_IS_5705_PLUS(sc))) CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); - val = BGE_WDMAMODE_ENABLE|BGE_WDMAMODE_ALL_ATTNS; + val = BGE_WDMAMODE_ENABLE | BGE_WDMAMODE_ALL_ATTNS; /* Enable host coalescing bug fix. */ if (sc->bge_asicrev == BGE_ASICREV_BCM5755 || sc->bge_asicrev == BGE_ASICREV_BCM5787) - val |= (1 << 29); + val |= 1 << 29; /* Turn on write DMA state machine */ CSR_WRITE_4(sc, BGE_WDMA_MODE, val); /* Turn on read DMA state machine */ CSR_WRITE_4(sc, BGE_RDMA_MODE, - BGE_RDMAMODE_ENABLE|BGE_RDMAMODE_ALL_ATTNS); + BGE_RDMAMODE_ENABLE | BGE_RDMAMODE_ALL_ATTNS); /* Turn on RX data completion state machine */ CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); @@ -1576,11 +1576,11 @@ CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF); CSR_WRITE_4(sc, BGE_SDI_STATS_CTL, - BGE_SDISTATSCTL_ENABLE|BGE_SDISTATSCTL_FASTER); + BGE_SDISTATSCTL_ENABLE | BGE_SDISTATSCTL_FASTER); /* ack/clear link change events */ - CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED| - BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE| + CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED | + BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE | BGE_MACSTAT_LINK_CHANGED); CSR_WRITE_4(sc, BGE_MI_STS, 0); @@ -1588,7 +1588,7 @@ if (sc->bge_flags & BGE_FLAG_TBI) { CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK); } else { - BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL|10<<16); + BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL | (10 << 16)); if (sc->bge_asicrev == BGE_ASICREV_BCM5700 && sc->bge_chipid != BGE_CHIPID_BCM5700_B2) CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, @@ -1602,8 +1602,8 @@ * It's not necessary on newer BCM chips - perhaps enabling link * state change attentions implies clearing pending attention. */ - CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED| - BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE| + CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED | + BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE | BGE_MACSTAT_LINK_CHANGED); /* Enable link state change attentions. */ @@ -1668,20 +1668,25 @@ char model[64], buf[96]; const struct bge_revision *br; const struct bge_vendor *v; - const char *pname; uint32_t id; id = pci_read_config(dev, BGE_PCI_MISC_CTL, 4) & BGE_PCIMISCCTL_ASICREV; br = bge_lookup_rev(id); v = bge_lookup_vendor(vid); - if (pci_get_vpd_ident(dev, &pname)) - snprintf(model, 64, "%s %s", - v->v_name, - br != NULL ? br->br_name : - "NetXtreme Ethernet Controller"); - else - snprintf(model, 64, "%s", pname); + { +#if __FreeBSD_version > 700024 + const char *pname; + + if (pci_get_vpd_ident(dev, &pname) == 0) + snprintf(model, 64, "%s", pname); + else +#endif + snprintf(model, 64, "%s %s", + v->v_name, + br != NULL ? br->br_name : + "NetXtreme Ethernet Controller"); + } snprintf(buf, 96, "%s, %sASIC rev. %#04x", model, br != NULL ? "" : "unknown ", id >> 16); device_set_desc_copy(dev, buf); @@ -1823,13 +1828,13 @@ /* * Allocate the parent bus DMA tag appropriate for PCI. */ - error = bus_dma_tag_create(bus_get_dma_tag(sc->bge_dev),/* parent */ + error = bus_dma_tag_create(bus_get_dma_tag(sc->bge_dev), /* parent */ 1, 0, /* alignment, boundary */ BUS_SPACE_MAXADDR, /* lowaddr */ BUS_SPACE_MAXADDR, /* highaddr */ NULL, NULL, /* filter, filterarg */ MAXBSIZE, BGE_NSEG_NEW, /* maxsize, nsegments */ - BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ + BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 0, /* flags */ NULL, NULL, /* lockfunc, lockarg */ &sc->bge_cdata.bge_parent_tag); @@ -2104,6 +2109,7 @@ return (0); } +#if __FreeBSD_version > 700025 /* * Return true if this device has more than one port. */ @@ -2151,6 +2157,7 @@ } return (can_use_msi); } +#endif static int bge_attach(device_t dev) @@ -2160,7 +2167,7 @@ uint32_t hwcfg = 0; uint32_t mac_tmp = 0; u_char eaddr[6]; - int error = 0, msicount, rid, trys, reg; + int error = 0, rid, trys, reg; sc = device_get_softc(dev); sc->bge_dev = dev; @@ -2172,7 +2179,7 @@ rid = BGE_PCI_BAR0; sc->bge_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, - RF_ACTIVE|PCI_RF_DENSE); + RF_ACTIVE | PCI_RF_DENSE); if (sc->bge_res == NULL) { device_printf (sc->bge_dev, "couldn't map memory\n"); @@ -2252,7 +2259,7 @@ #else if (BGE_IS_5705_PLUS(sc)) { reg = pci_read_config(dev, BGE_PCIE_CAPID_REG, 4); - if ((reg & 0xff) == BGE_PCIE_CAPID) + if ((reg & 0xFF) == BGE_PCIE_CAPID) sc->bge_flags |= BGE_FLAG_PCIE; } else { /* @@ -2265,22 +2272,30 @@ } #endif - /* - * Allocate the interrupt, using MSI if possible. These devices - * support 8 MSI messages, but only the first one is used in - * normal operation. - */ - if (bge_can_use_msi(sc)) { - msicount = pci_msi_count(dev); - if (msicount > 1) - msicount = 1; - } else - msicount = 0; - if (msicount == 1 && pci_alloc_msi(dev, &msicount) == 0) { - rid = 1; - sc->bge_flags |= BGE_FLAG_MSI; - } else - rid = 0; +#if __FreeBSD_version > 700025 + { + int msicount; + + /* + * Allocate the interrupt, using MSI if possible. These devices + * support 8 MSI messages, but only the first one is used in + * normal operation. + */ + if (bge_can_use_msi(sc)) { + msicount = pci_msi_count(dev); + if (msicount > 1) + msicount = 1; + } else + msicount = 0; + if (msicount == 1 && pci_alloc_msi(dev, &msicount) == 0) { + rid = 1; + sc->bge_flags |= BGE_FLAG_MSI; + } else + rid = 0; + } +#else + rid = 0; +#endif sc->bge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, RF_SHAREABLE | RF_ACTIVE); @@ -2337,11 +2352,11 @@ /* * Get station address from the EEPROM. */ - mac_tmp = bge_readmem_ind(sc, 0x0c14); - if ((mac_tmp >> 16) == 0x484b) { + mac_tmp = bge_readmem_ind(sc, 0x0C14); + if ((mac_tmp >> 16) == 0x484B) { eaddr[0] = (u_char)(mac_tmp >> 8); eaddr[1] = (u_char)mac_tmp; - mac_tmp = bge_readmem_ind(sc, 0x0c18); + mac_tmp = bge_readmem_ind(sc, 0x0C18); eaddr[2] = (u_char)(mac_tmp >> 24); eaddr[3] = (u_char)(mac_tmp >> 16); eaddr[4] = (u_char)(mac_tmp >> 8); @@ -2395,7 +2410,10 @@ IFQ_SET_READY(&ifp->if_snd); ifp->if_hwassist = BGE_CSUM_FEATURES; ifp->if_capabilities = IFCAP_HWCSUM | IFCAP_VLAN_HWTAGGING | - IFCAP_VLAN_MTU | IFCAP_VLAN_HWCSUM; + IFCAP_VLAN_MTU; +#ifdef IFCAP_VLAN_HWCSUM + ifp->if_capabilities |= IFCAP_VLAN_HWCSUM; +#endif ifp->if_capenable = ifp->if_capabilities; #ifdef DEVICE_POLLING ifp->if_capabilities |= IFCAP_POLLING; @@ -2441,13 +2459,13 @@ sc->bge_flags |= BGE_FLAG_TBI; if (sc->bge_flags & BGE_FLAG_TBI) { - ifmedia_init(&sc->bge_ifmedia, IFM_IMASK, - bge_ifmedia_upd, bge_ifmedia_sts); - ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL); - ifmedia_add(&sc->bge_ifmedia, - IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL); - ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL); - ifmedia_set(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO); + ifmedia_init(&sc->bge_ifmedia, IFM_IMASK, bge_ifmedia_upd, + bge_ifmedia_sts); + ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_1000_SX, 0, NULL); + ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_1000_SX | IFM_FDX, + 0, NULL); + ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL); + ifmedia_set(&sc->bge_ifmedia, IFM_ETHER | IFM_AUTO); sc->bge_ifmedia.ifm_media = sc->bge_ifmedia.ifm_cur->ifm_media; } else { /* @@ -2466,7 +2484,8 @@ bge_ifmedia_upd, bge_ifmedia_sts)) { if (trys++ < 4) { device_printf(sc->bge_dev, "Try again\n"); - bge_miibus_writereg(sc->bge_dev, 1, MII_BMCR, BMCR_RESET); + bge_miibus_writereg(sc->bge_dev, 1, MII_BMCR, + BMCR_RESET); goto again; } @@ -2504,8 +2523,13 @@ /* * Hookup IRQ last. */ +#if __FreeBSD_version > 700030 error = bus_setup_intr(dev, sc->bge_irq, INTR_TYPE_NET | INTR_MPSAFE, NULL, bge_intr, sc, &sc->bge_intrhand); +#else + error = bus_setup_intr(dev, sc->bge_irq, INTR_TYPE_NET | INTR_MPSAFE, + bge_intr, sc, &sc->bge_intrhand); +#endif if (error) { bge_detach(dev); @@ -2567,8 +2591,10 @@ bus_release_resource(dev, SYS_RES_IRQ, sc->bge_flags & BGE_FLAG_MSI ? 1 : 0, sc->bge_irq); +#if __FreeBSD_version > 700025 if (sc->bge_flags & BGE_FLAG_MSI) pci_release_msi(dev); +#endif if (sc->bge_res != NULL) bus_release_resource(dev, SYS_RES_MEMORY, @@ -2607,8 +2633,8 @@ pcistate = pci_read_config(dev, BGE_PCI_PCISTATE, 4); pci_write_config(dev, BGE_PCI_MISC_CTL, - BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR| - BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_PCISTATE_RW, 4); + BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR | + BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW, 4); /* Disable fastboot on controllers that support it. */ if (sc->bge_asicrev == BGE_ASICREV_BCM5752 || @@ -2626,16 +2652,16 @@ */ bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER); - reset = BGE_MISCCFG_RESET_CORE_CLOCKS|(65<<1); + reset = BGE_MISCCFG_RESET_CORE_CLOCKS | BGE_32BITTIME_66MHZ; /* XXX: Broadcom Linux driver. */ if (sc->bge_flags & BGE_FLAG_PCIE) { - if (CSR_READ_4(sc, 0x7e2c) == 0x60) /* PCIE 1.0 */ - CSR_WRITE_4(sc, 0x7e2c, 0x20); + if (CSR_READ_4(sc, 0x7E2C) == 0x60) /* PCIE 1.0 */ + CSR_WRITE_4(sc, 0x7E2C, 0x20); if (sc->bge_chipid != BGE_CHIPID_BCM5750_A0) { /* Prevent PCIE link training during global reset */ - CSR_WRITE_4(sc, BGE_MISC_CFG, (1<<29)); - reset |= (1<<29); + CSR_WRITE_4(sc, BGE_MISC_CFG, 1 << 29); + reset |= 1 << 29; } } @@ -2657,23 +2683,23 @@ uint32_t v; DELAY(500000); /* wait for link training to complete */ - v = pci_read_config(dev, 0xc4, 4); - pci_write_config(dev, 0xc4, v | (1<<15), 4); + v = pci_read_config(dev, 0xC4, 4); + pci_write_config(dev, 0xC4, v | (1 << 15), 4); } /* * Set PCIE max payload size to 128 bytes and clear error * status. */ - pci_write_config(dev, 0xd8, 0xf5000, 4); + pci_write_config(dev, 0xD8, 0xF5000, 4); } /* Reset some of the PCI state that got zapped by reset. */ pci_write_config(dev, BGE_PCI_MISC_CTL, - BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR| - BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_PCISTATE_RW, 4); + BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR | + BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW, 4); pci_write_config(dev, BGE_PCI_CACHESZ, cachesize, 4); pci_write_config(dev, BGE_PCI_CMD, command, 4); - write_op(sc, BGE_MISC_CFG, (65 << 1)); + write_op(sc, BGE_MISC_CFG, BGE_32BITTIME_66MHZ); /* Re-enable MSI, if neccesary, and enable the memory arbiter. */ if (BGE_IS_5714_FAMILY(sc)) { @@ -2725,12 +2751,12 @@ } if (sc->bge_flags & BGE_FLAG_PCIE) { - reset = bge_readmem_ind(sc, 0x7c00); - bge_writemem_ind(sc, 0x7c00, reset | (1 << 25)); + reset = bge_readmem_ind(sc, 0x7C00); + bge_writemem_ind(sc, 0x7C00, reset | (1 << 25)); } /* Fix up byte swapping. */ - CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS| + CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS | BGE_MODECTL_BYTESWAP_DATA); /* Tell the ASF firmware we are up */ @@ -2758,8 +2784,8 @@ sc->bge_chipid != BGE_CHIPID_BCM5750_A0) { uint32_t v; - v = CSR_READ_4(sc, 0x7c00); - CSR_WRITE_4(sc, 0x7c00, v | (1<<25)); + v = CSR_READ_4(sc, 0x7C00); + CSR_WRITE_4(sc, 0x7C00, v | (1 << 25)); } DELAY(10000); @@ -2887,7 +2913,7 @@ if (ifp->if_capenable & IFCAP_RXCSUM) { if (cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) { m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; - if ((cur_rx->bge_ip_csum ^ 0xffff) == 0) + if ((cur_rx->bge_ip_csum ^ 0xFFFF) == 0) m->m_pkthdr.csum_flags |= CSUM_IP_VALID; } if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM && @@ -2904,8 +2930,14 @@ * attach that information to the packet. */ if (have_tag) { +#if __FreeBSD_version > 700022 m->m_pkthdr.ether_vtag = vlan_tag; m->m_flags |= M_VLANTAG; +#else + VLAN_INPUT_TAG_NEW(ifp, m, vlan_tag); + if (m == NULL) + continue; +#endif } BGE_UNLOCK(sc); @@ -2953,7 +2985,7 @@ bus_dmamap_sync(sc->bge_cdata.bge_tx_ring_tag, sc->bge_cdata.bge_tx_ring_map, - BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); + BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); /* * Go through our tx ring and free mbufs for those * frames that have been sent. @@ -3007,7 +3039,7 @@ bus_dmamap_sync(sc->bge_cdata.bge_status_tag, sc->bge_cdata.bge_status_map, BUS_DMASYNC_PREREAD); - /* Note link event. It will be processed by POLL_AND_CHECK_STATUS cmd */ + /* Note link event. It will be processed by POLL_AND_CHECK_STATUS. */ if (statusword & BGE_STATFLAG_LINKSTATE_CHANGED) sc->bge_link_evt++; @@ -3114,7 +3146,7 @@ bge_writemem_ind(sc, BGE_SOFTWARE_GENNCOMM_FW_LEN, 4); bge_writemem_ind(sc, BGE_SOFTWARE_GENNCOMM_FW_DATA, 3); CSR_WRITE_4(sc, BGE_CPU_EVENT, - CSR_READ_4(sc, BGE_CPU_EVENT) != (1 << 14)); + CSR_READ_4(sc, BGE_CPU_EVENT) | (1 << 14)); } } } @@ -3333,12 +3365,24 @@ /* ... and put VLAN tag into first segment. */ d = &sc->bge_ldata.bge_tx_ring[*txidx]; +#if __FreeBSD_version > 700022 if (m->m_flags & M_VLANTAG) { d->bge_flags |= BGE_TXBDFLAG_VLAN_TAG; d->bge_vlan_tag = m->m_pkthdr.ether_vtag; } else d->bge_vlan_tag = 0; +#else + { + struct m_tag *mtag; + if ((mtag = VLAN_OUTPUT_TAG(sc->bge_ifp, m)) != NULL) { + d->bge_flags |= BGE_TXBDFLAG_VLAN_TAG; + d->bge_vlan_tag = VLAN_TAG_VALUE(mtag); + } else + d->bge_vlan_tag = 0; + } +#endif + /* * Insure that the map for this transmission * is placed at the array index of the last descriptor @@ -3420,7 +3464,11 @@ * If there's a BPF listener, bounce a copy of this frame * to him. */ +#ifdef ETHER_BPF_MTAP ETHER_BPF_MTAP(ifp, m_head); +#else + BPF_MTAP(ifp, m_head); +#endif } if (count == 0) @@ -3626,11 +3674,11 @@ uint32_t sgdig; CSR_WRITE_4(sc, BGE_TX_TBI_AUTONEG, 0); sgdig = CSR_READ_4(sc, BGE_SGDIG_CFG); - sgdig |= BGE_SGDIGCFG_AUTO| - BGE_SGDIGCFG_PAUSE_CAP| + sgdig |= BGE_SGDIGCFG_AUTO | + BGE_SGDIGCFG_PAUSE_CAP | BGE_SGDIGCFG_ASYM_PAUSE; CSR_WRITE_4(sc, BGE_SGDIG_CFG, - sgdig|BGE_SGDIGCFG_SEND); + sgdig | BGE_SGDIGCFG_SEND); DELAY(5); CSR_WRITE_4(sc, BGE_SGDIG_CFG, sgdig); } @@ -3805,7 +3853,9 @@ ifp->if_hwassist = BGE_CSUM_FEATURES; else ifp->if_hwassist = 0; +#ifdef VLAN_CAPABILITIES VLAN_CAPABILITIES(ifp); +#endif } break; default: >>> TRUNCATED FOR MAIL (1000 lines) <<<
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