From owner-freebsd-hardware  Wed May 15 07:25:51 1996
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To: Sean Eric Fagan <sef@kithrup.com>
cc: mmead@Glock.COM, hardware@FreeBSD.org
Subject: Re: Triton chipset with 256k cache caches 32M only? 
In-reply-to: Your message of "Tue, 14 May 1996 11:55:13 PDT."
             <199605141855.LAA00480@kithrup.com> 
From: David Greenman <davidg@Root.COM>
Reply-To: davidg@Root.COM
Date: Wed, 15 May 1996 07:25:43 -0700
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>I'm assuming that, in ECC mode, the chipset always makes sure 64 bits are
>fetched; with one bit of parity per 8-bit byte, that gives you 8 bits of
>parity bits per 64-bit longword; that leaves a couple of extra bits more
>than ECC requires.

   ECC requires 8 syndrome bits for 64bits of data; there are no extra bits.

-DG

David Greenman
Core-team/Principal Architect, The FreeBSD Project