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Date:      Tue, 30 Jun 2015 15:02:01 GMT
From:      mihai@FreeBSD.org
To:        svn-soc-all@FreeBSD.org
Subject:   socsvn commit: r287759 - in soc2015/mihai/bhyve-on-arm-head/sys: arm/vmm modules/vmm-arm
Message-ID:  <201506301502.t5UF21iS050324@socsvn.freebsd.org>

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Author: mihai
Date: Tue Jun 30 15:02:00 2015
New Revision: 287759
URL: http://svnweb.FreeBSD.org/socsvn/?view=rev&rev=287759

Log:
  sys: arm: vmm: add save/restore low-level mechanism for a guest OS

Added:
  soc2015/mihai/bhyve-on-arm-head/sys/arm/vmm/hyp_genassym.c
Modified:
  soc2015/mihai/bhyve-on-arm-head/sys/arm/vmm/arm.h
  soc2015/mihai/bhyve-on-arm-head/sys/arm/vmm/hyp.S
  soc2015/mihai/bhyve-on-arm-head/sys/arm/vmm/hyp.h
  soc2015/mihai/bhyve-on-arm-head/sys/modules/vmm-arm/Makefile

Modified: soc2015/mihai/bhyve-on-arm-head/sys/arm/vmm/arm.h
==============================================================================
--- soc2015/mihai/bhyve-on-arm-head/sys/arm/vmm/arm.h	Tue Jun 30 14:17:02 2015	(r287758)
+++ soc2015/mihai/bhyve-on-arm-head/sys/arm/vmm/arm.h	Tue Jun 30 15:02:00 2015	(r287759)
@@ -1,9 +1,75 @@
 #include "mmu.h"
+#include <machine/reg.h>
+
+struct hypctx {
+	struct hyp*	hyp;
+
+	struct reg	regs;
+
+	uint32_t	hcr;
+
+	uint32_t	midr;
+	uint32_t	mpidr;
+
+	uint32_t	sp_und;
+	uint32_t	lr_und;
+	uint32_t	spsr_und;
+
+	uint32_t	sp_svc;
+	uint32_t	lr_svc;
+	uint32_t	spsr_svc;
+
+	uint32_t	sp_abt;
+	uint32_t	lr_abt;
+	uint32_t	spsr_abt;
+
+	uint32_t	sp_irq;
+	uint32_t	lr_irq;
+	uint32_t	spsr_irq;
+
+	uint32_t	sp_fiq;
+	uint32_t	lr_fiq;
+	uint32_t	spsr_fiq;
+	uint32_t	r8_fiq;
+	uint32_t	r9_fiq;
+	uint32_t	r10_fiq;
+	uint32_t	r11_fiq;
+	uint32_t	r12_fiq;
+
+	uint32_t	cp15_sctlr;
+	uint32_t	cp15_cpacr;
+	uint32_t	cp15_ttbcr;
+	uint32_t	cp15_dacr;
+	uint64_t	cp15_ttbr0;
+	uint64_t	cp15_ttbr1;
+	uint32_t	cp15_prrr;
+	uint32_t	cp15_nmrr;
+	uint32_t	cp15_csselr;
+	uint32_t	cp15_cid;
+	uint32_t	cp15_tid_urw;
+	uint32_t	cp15_tid_uro;
+	uint32_t	cp15_tid_priv;
+	uint32_t	cp15_dfsr;
+	uint32_t	cp15_ifsr;
+	uint32_t	cp15_adfsr;
+	uint32_t	cp15_aifsr;
+	uint32_t	cp15_dfar;
+	uint32_t	cp15_ifar;
+	uint32_t	cp15_vbar;
+	uint32_t	cp15_cntkctl;
+	uint64_t	cp15_par;
+	uint32_t	cp15_amair0;
+	uint32_t	cp15_amair1;
+
+};
 
 struct hyp {
 	lpae_pd_entry_t l1pd[2 * LPAE_L1_ENTRIES];
+	lpae_pd_entry_t	vttbr;
+	struct hypctx	ctx[VM_MAXCPU];
 	struct vm	*vm;
 };
+CTASSERT((offsetof(struct hyp, l1pd) & PAGE_MASK) == 0);
 
 uint64_t vmm_call_hyp(void *hyp_func_addr, ...);
 

Modified: soc2015/mihai/bhyve-on-arm-head/sys/arm/vmm/hyp.S
==============================================================================
--- soc2015/mihai/bhyve-on-arm-head/sys/arm/vmm/hyp.S	Tue Jun 30 14:17:02 2015	(r287758)
+++ soc2015/mihai/bhyve-on-arm-head/sys/arm/vmm/hyp.S	Tue Jun 30 15:02:00 2015	(r287759)
@@ -6,9 +6,9 @@
 #include <machine/sysreg.h>
 #include <machine/cpuconf.h>
 
+#include "hyp_assym.h"
 #include "hyp.h"
 
-
 .text
 	.globl	hyp_code_start
 	.globl	hyp_code_end
@@ -21,6 +21,108 @@
 	hvc	#0
 	bx	lr
 END(vmm_call_hyp)
+/*
+ * int hyp_enter_guest(struct *hyp_vmxctx);
+ * - r0 pointer to the struct hyp_vmxctx
+ */
+ENTRY(hyp_enter_guest)
+	mcr	p15, 4, r0, c13, c0, 2		@ Store hyp_vmxctx into HTPIDR
+	save_host_regs
+
+	/* Save HOST CP15 registers */
+	load_cp15_regs_batch1				@ Load in r2-r12 CP15 regs
+	push {r2-r12}
+	load_cp15_regs_batch2				@ Load in r2-r12 CP15 regs
+	push {r2-r12}
+	load_cp15_regs_batch3				@ Load in r2-r6 CP15 regs
+	push {r2-r6}
+	
+	/* Load GUEST CP15 registers */
+	load_guest_cp15_regs_batch1
+	store_cp15_regs_batch1
+	load_guest_cp15_regs_batch2
+	store_cp15_regs_batch2
+	load_guest_cp15_regs_batch3
+	store_cp15_regs_batch3
+	
+	/* Enable stage-2 MMU, trap interrupts */
+	ldr	r1, [r0, #HYPCTX_HCR]
+	mcr	p15, 4, r1, c1, c1, 0
+
+	/* Set MIDR and MPIDR for the Guest */
+	ldr	r1, [r0, #HYPCTX_MIDR]
+	mcr	p15, 4, r1, c0, c0, 0
+	ldr	r1, [r0, #HYPCTX_MPIDR]
+	mcr	p15, 4, r1, c0, c0, 5
+
+	/* Set VTTBR for stage-2 translation */
+	ldr	r1, [r0, #HYPCTX_HYP]
+	add	r1, r1, #HYP_VTTBR
+	ldrd	r2, r3, [r1]
+	mcrr	p15, 6, r2, r3, c2
+
+	/* Trap access to the CP10/CP11 [vfp/simd] */
+	mrc     p15, 4, r1, c1, c1, 2
+	ldr	r2, =(HCPTR_TTA | HCPTR_TCP(10) | HCPTR_TCP(11))
+	orr     r1, r1, r2
+	mcr     p15, 4, r1, c1, c1, 2
+
+
+	restore_guest_regs
+
+	eret
+hyp_exit_guest:
+	/* 
+	 * r0 - hypctx pointer
+	 * r1 - exception code
+	 * guest r0-r2 saved on stack when trapping in HYP mode 
+	 */
+	
+	save_guest_regs
+	
+	/* Disable trap access to the CP10/CP11 [vfp/simd] */
+	mrc     p15, 4, r2, c1, c1, 2
+	ldr	r3, =(HCPTR_TTA | HCPTR_TCP(10) | HCPTR_TCP(11))
+	bic     r2, r2, r3
+	mcr     p15, 4, r2, c1, c1, 2
+
+	/* Set VTTBR to 0 (VMID to 0) */
+	mov	r2, #0
+	mov	r3, #0
+	mcrr    p15, 6, r2, r3, c2
+
+	/* Set MIDR and MPIDR at hardware values */
+	mrc     p15, 0, r2, c0, c0, 0
+	mcr     p15, 4, r2, c0, c0, 0
+	mrc     p15, 0, r2, c0, c0, 5
+	mcr     p15, 4, r2, c0, c0, 5
+
+	/* Disable all traps - HCR */
+	mov	r2, #0
+	mcr	p15, 4, r1, c1, c1, 0
+
+
+	/* Save guest CP15 registers */
+	load_cp15_regs_batch1
+	store_guest_cp15_regs_batch1
+	load_cp15_regs_batch2
+	store_guest_cp15_regs_batch2
+	load_cp15_regs_batch3
+	store_guest_cp15_regs_batch3
+
+	/* Load HOST CP15 registers in reverse order from the stack */
+	pop {r2-r6}
+	store_cp15_regs_batch3			@ Load in r2-r6 CP15 regs
+	pop {r2-r12}
+	store_cp15_regs_batch2			@ Load in r2-r12 CP15 regs
+	pop {r2-r12}
+	store_cp15_regs_batch1			@ Load in r2-r12 CP15 regs
+
+	restore_host_regs
+
+	mov	r0, r1				@ r0 must hold the return value
+	bx	lr				@ go back to the host ("Returned from function" comment)
+END(hyp_enter_guest)
 
 /* 
  * void vmm_stub_install(void *hypervisor_stub_vect);
@@ -72,7 +174,7 @@
 hyp_init_hvc:
 	mcr     p15, 4, r0, c12, c0, 0	@ set HVBAR to the new vector
 	mov     sp, r1			@ set SP. r1 contains the stack pointer
-	mcrr	p15, 4, r2, r3, c2	@ set the HTTBR (r2 is the low word, r3 is the low word)
+	mcrr	p15, 4, r2, r3, c2	@ set the HTTBR (r2 is the low word, r3 is the high word)
 	isb
 
 	@ Set HTCR.T0SZ=0 so x=5 (ARM man: B4.1.76)
@@ -184,18 +286,27 @@
 	mrs	lr, SPSR
 	push	{lr}
 
+	/* Build param list for the function pointer in r0 */
 	mov	lr, r0
 	mov	r0, r1
 	mov	r1, r2
 	mov	r2, r3
 	blx	lr
+	/* Returned from function */
 	pop	{lr}
 	msr	SPSR_csxf, lr
 	pop	{lr}
 	eret
 
 guest_trap:
-	b	loop
+	/* Load hypctx in r0 from HTPIDR*/
+	mrc	p15, 4, r0, c13, c0, 2
+	mov	r1, #EXCEPTION_HVC
+
+	// TODO: check exception cause and load status registers in hypctx
+
+	b	hyp_exit_guest
+
 	.align
 hyp_fiq:
 	b loop
@@ -221,7 +332,10 @@
 	eret
 
 guest_bad_exception:
-	b loop
+	/* Load hypctx pointer to r0 */
+	mrc	p15, 4, r0, c13, c0, 2
+	// TODO: load HSR in VCPU
+	b	hyp_exit_guest
 END(handle_bad_exception)
 
 loop:

Modified: soc2015/mihai/bhyve-on-arm-head/sys/arm/vmm/hyp.h
==============================================================================
--- soc2015/mihai/bhyve-on-arm-head/sys/arm/vmm/hyp.h	Tue Jun 30 14:17:02 2015	(r287758)
+++ soc2015/mihai/bhyve-on-arm-head/sys/arm/vmm/hyp.h	Tue Jun 30 15:02:00 2015	(r287759)
@@ -26,6 +26,12 @@
 #define HSCTLR_A	(1 << 1)
 #define HSCTLR_M	(1 << 0)
 #define HSCTLR_MASK	(HSCTLR_M | HSCTLR_A | HSCTLR_C | HSCTLR_I | HSCTLR_WXN | HSCTLR_FI | HSCTLR_EE | HSCTLR_TE)
+/* Hyp Coprocessor Trap Register */
+#define HCPTR_TCP(x)	(1 << x)
+#define HCPTR_TCP_MASK	(0x3fff)
+#define HCPTR_TASE	(1 << 15)
+#define HCPTR_TTA	(1 << 20)
+#define HCPTR_TCPAC	(1 << 31)
 
 /* TTBCR and HTCR Registers bits */
 #define TTBCR_EAE	(1 << 31)
@@ -55,6 +61,67 @@
 #define VTCR_SL_L2	(0 << 6)	/* Starting-level: 2 */
 #define VTCR_SL_L1	(1 << 6)	/* Starting-level: 1 */
 
+/* Hyp Configuration Register (HCR) bits */
+#define HCR_TGE		(1 << 27)
+#define HCR_TVM		(1 << 26)
+#define HCR_TTLB	(1 << 25)
+#define HCR_TPU		(1 << 24)
+#define HCR_TPC		(1 << 23)
+#define HCR_TSW		(1 << 22)
+#define HCR_TAC		(1 << 21)
+#define HCR_TIDCP	(1 << 20)
+#define HCR_TSC		(1 << 19)
+#define HCR_TID3	(1 << 18)
+#define HCR_TID2	(1 << 17)
+#define HCR_TID1	(1 << 16)
+#define HCR_TID0	(1 << 15)
+#define HCR_TWE		(1 << 14)
+#define HCR_TWI		(1 << 13)
+#define HCR_DC		(1 << 12)
+#define HCR_BSU		(3 << 10)
+#define HCR_BSU_IS	(1 << 10)
+#define HCR_FB		(1 << 9)
+#define HCR_VA		(1 << 8)
+#define HCR_VI		(1 << 7)
+#define HCR_VF		(1 << 6)
+#define HCR_AMO		(1 << 5)
+#define HCR_IMO		(1 << 4)
+#define HCR_FMO		(1 << 3)
+#define HCR_PTW		(1 << 2)
+#define HCR_SWIO	(1 << 1)
+#define HCR_VM		1
+/* 
+ * B4.1.65 HCR, Hyp Configuration Register,
+ *
+ * HCR_TSW - Trap set/way cache maintenance operations
+ * HCR_TAC - Trap ACTLR accessses
+ * HCR_TIDCP - Trap lockdown
+ * HCR_TSC - Trap SMC instruction
+ * HCR_TWE - Trap WFE instruction
+ * HCR_TWI - Trap WFI instruction
+ * HCR_BSU_IS -
+ * HCR_FB - Force broadcast TLB/branch predictor/ cache invalidate across ISB
+ * HCR_AMO - Overrides the CPSR.A bit, and enables signaling by the VA bit
+ * HCR_IMO - Overrides the CPSR.I bit, and enables signaling by the VI bit
+ * HCR_FMO - Overrides the CPSR.F bit, and enables signaling by the VF bit
+ * HCR_SWIO - Set/way invalidation override
+ * HCR_VM - Virtualization MMU enable (stage 2)
+ */
+#define HCR_GUEST_MASK (HCR_TSW | HCR_TAC | HCR_TIDCP | \
+    HCR_TSC | HCR_TWE | HCR_TWI | HCR_BSU_IS | HCR_FB | \
+    HCR_AMO | HCR_IMO | HCR_FMO | HCR_SWIO | HCR_VM
+
+/* Hyp Coprocessor Trap Register */
+#define HCPTR_TCP(x)	(1 << x)
+#define HCPTR_TCP_MASK	(0x3fff)
+#define HCPTR_TASE	(1 << 15)
+#define HCPTR_TTA	(1 << 20)
+#define HCPTR_TCPAC	(1 << 31)
+
+/* Hyp System Trap Register */
+#define HSTR_T(x)	(1 << x)
+#define HSTR_TTEE	(1 << 16)
+#define HSTR_TJDBX	(1 << 17)
 
 /*
  * Memory region attributes for LPAE (defined in pgtable-3level.h):
@@ -79,4 +146,260 @@
 #define HMAIR0		MAIR0
 #define HMAIR1		MAIR1
 
+#define	HYPCTX_REGS_R(x)	(HYPCTX_REGS + x * 4)
+
+/* Banked registers */
+#define SAVE_GUEST_BANKED_REG(reg)		\
+	mrs	r2, reg;			\
+	str	r2, [r0, #HYPCTX_##reg]
+#define SAVE_GUEST_BANKED_MODE(mode)		\
+	SAVE_GUEST_BANKED_REG(SP_##mode);	\
+	SAVE_GUEST_BANKED_REG(LR_##mode);	\
+	SAVE_GUEST_BANKED_REG(SPSR_##mode)
+
+#define RESTORE_GUEST_BANKED_REG(reg)		\
+	ldr	r2, [r0, #HYPCTX_##reg];	\
+	msr	reg, r2
+#define RESTORE_GUEST_BANKED_MODE(mode)		\
+	RESTORE_GUEST_BANKED_REG(SP_##mode);	\
+	RESTORE_GUEST_BANKED_REG(LR_##mode);	\
+	RESTORE_GUEST_BANKED_REG(SPSR_##mode)
+
+#define	save_guest_regs						\
+	/* r0 - address of the hypctx */			\
+	add	r2, r0, #HYPCTX_REGS_R(3);			\
+	stm	r2, {r3-r12};					\
+	pop	{r3-r5};	@ Get r0-r2 from the stack	\
+	add	r2, r0, #HYPCTX_REGS_R(0);			\
+	stm	r2, {r3-r5};					\
+								\
+	str	lr, [r0, #HYPCTX_REGS_LR];			\
+	mrs	r2, SP_usr;					\
+	str	r2, [r0, #HYPCTX_REGS_SP];			\
+								\
+	mrs	r2, ELR_hyp;					\
+	str	r2, [r0, #HYPCTX_REGS_PC];			\
+	mrs	r2, spsr;					\
+	str	r2, [r0, #HYPCTX_REGS_CPSR];			\
+								\
+	SAVE_GUEST_BANKED_MODE(svc);				\
+	SAVE_GUEST_BANKED_MODE(abt);				\
+	SAVE_GUEST_BANKED_MODE(und);				\
+	SAVE_GUEST_BANKED_MODE(irq);				\
+	SAVE_GUEST_BANKED_MODE(fiq);				\
+	SAVE_GUEST_BANKED_REG(r8_fiq);				\
+	SAVE_GUEST_BANKED_REG(r9_fiq);				\
+	SAVE_GUEST_BANKED_REG(r10_fiq);				\
+	SAVE_GUEST_BANKED_REG(r11_fiq);				\
+	SAVE_GUEST_BANKED_REG(r12_fiq)
+
+#define	restore_guest_regs					\
+	/* r0 - address of the hypctx */			\
+	RESTORE_GUEST_BANKED_MODE(svc);				\
+	RESTORE_GUEST_BANKED_MODE(abt);				\
+	RESTORE_GUEST_BANKED_MODE(und);				\
+	RESTORE_GUEST_BANKED_MODE(irq);				\
+	RESTORE_GUEST_BANKED_MODE(fiq);				\
+	RESTORE_GUEST_BANKED_REG(r8_fiq);			\
+	RESTORE_GUEST_BANKED_REG(r9_fiq);			\
+	RESTORE_GUEST_BANKED_REG(r10_fiq);			\
+	RESTORE_GUEST_BANKED_REG(r11_fiq);			\
+	RESTORE_GUEST_BANKED_REG(r12_fiq);			\
+								\
+	ldr	r2, [r0, #HYPCTX_REGS_PC];			\
+	msr	ELR_hyp, r2;					\
+	ldr	r2, [r0, #HYPCTX_REGS_CPSR];			\
+	msr	SPSR_cxsf, r2;					\
+								\
+	ldr	lr, [r0, #HYPCTX_REGS_LR];			\
+	ldr	r2, [r0, #HYPCTX_REGS_SP];			\
+	msr	SP_usr, r2;					\
+								\
+	add	r2, r0, #HYPCTX_REGS_R(0);			\
+	ldm	r2, {r0-r12}
+
+
+#define SAVE_HOST_BANKED_REG(reg)		\
+	mrs	r2, reg;			\
+	push	{r2}
+#define SAVE_HOST_BANKED_MODE(mode)		\
+	SAVE_HOST_BANKED_REG(SP_##mode);	\
+	SAVE_HOST_BANKED_REG(LR_##mode);	\
+	SAVE_HOST_BANKED_REG(SPSR_##mode)
+
+#define RESTORE_HOST_BANKED_REG(reg)		\
+	pop	{r2};				\
+	msr	reg, r2
+#define RESTORE_HOST_BANKED_MODE(mode)		\
+	RESTORE_HOST_BANKED_REG(SPSR_##mode);	\
+	RESTORE_HOST_BANKED_REG(LR_##mode);	\
+	RESTORE_HOST_BANKED_REG(SP_##mode)
+
+#define	save_host_regs						\
+	/* SPSR was saved when entered HYP mode */		\
+	mrs	r2, ELR_hyp;					\
+	push	{r2};						\
+								\
+	push	{r4-r12};					\
+	mrs	r2, SP_usr;					\
+	push	{r2};						\
+	push	{lr};						\
+								\
+	SAVE_HOST_BANKED_MODE(svc);				\
+	SAVE_HOST_BANKED_MODE(abt);				\
+	SAVE_HOST_BANKED_MODE(und);				\
+	SAVE_HOST_BANKED_MODE(irq);				\
+	SAVE_HOST_BANKED_MODE(fiq);				\
+	SAVE_HOST_BANKED_REG(r8_fiq);				\
+	SAVE_HOST_BANKED_REG(r9_fiq);				\
+	SAVE_HOST_BANKED_REG(r10_fiq);				\
+	SAVE_HOST_BANKED_REG(r11_fiq);				\
+	SAVE_HOST_BANKED_REG(r12_fiq)
+
+#define	restore_host_regs					\
+	RESTORE_HOST_BANKED_REG(r12_fiq);			\
+	RESTORE_HOST_BANKED_REG(r11_fiq);			\
+	RESTORE_HOST_BANKED_REG(r10_fiq);			\
+	RESTORE_HOST_BANKED_REG(r9_fiq);			\
+	RESTORE_HOST_BANKED_REG(r8_fiq);			\
+	RESTORE_HOST_BANKED_MODE(fiq);				\
+	RESTORE_HOST_BANKED_MODE(irq);				\
+	RESTORE_HOST_BANKED_MODE(und);				\
+	RESTORE_HOST_BANKED_MODE(abt);				\
+	RESTORE_HOST_BANKED_MODE(svc);				\
+								\
+	pop	{lr};						\
+	pop	{r2};						\
+	msr	SP_usr, r2;					\
+	pop	{r4-r12};					\
+								\
+	pop	{r2};						\
+	msr	ELR_hyp, r2
+
+#define	load_cp15_regs_batch1					\
+	mrc	p15, 0, r2, c1, c0, 0;		@ SCTLR		\
+	mrc	p15, 0, r3, c1, c0, 2;		@ CPACR		\
+	mrc	p15, 0, r4, c2, c0, 2;		@ TTBCR		\
+	mrc	p15, 0, r5, c3, c0, 0;		@ DACR		\
+	mrrc	p15, 0, r6, r7, c2;		@ TTBR 0	\
+	mrrc	p15, 1, r8, r9, c2;		@ TTBR 1	\
+	mrc	p15, 0, r10, c10, c2, 0;	@ PRRR		\
+	mrc	p15, 0, r11, c10, c2, 1;	@ NMRR		\
+	mrc	p15, 2, r12, c0, c0, 0		@ CSSELR
+
+#define	load_cp15_regs_batch2					\
+	mrc	p15, 0, r2, c13, c0, 1;		@ CID		\
+	mrc	p15, 0, r3, c13, c0, 2;		@ TID_URW	\
+	mrc	p15, 0, r4, c13, c0, 3;		@ TID_URO	\
+	mrc	p15, 0, r5, c13, c0, 4;		@ TID_PRIV	\
+	mrc	p15, 0, r6, c5, c0, 0;		@ DFSR		\
+	mrc	p15, 0, r7, c5, c0, 1;		@ IFSR		\
+	mrc	p15, 0, r8, c5, c1, 0;		@ ADFSR		\
+	mrc	p15, 0, r9, c5, c1, 1;		@ AIFSR		\
+	mrc	p15, 0, r10, c6, c0, 0;		@ DFAR		\
+	mrc	p15, 0, r11, c6, c0, 2;		@ IFAR		\
+	mrc	p15, 0, r12, c12, c0, 0		@ VBAR
+
+#define	load_cp15_regs_batch3					\
+	mrc	p15, 0, r2, c14, c1, 0;		@ CNTKCTL	\
+	mrrc	p15, 0, r3, r4, c7;		@ PAR		\
+	mrc	p15, 0, r5, c10, c3, 0;		@ AMAIR0	\
+	mrc	p15, 0, r6, c10, c3, 1		@ AMAIR1
+
+#define	store_cp15_regs_batch1					\
+	mcr	p15, 0, r2, c1, c0, 0;		@ SCTLR		\
+	mcr	p15, 0, r3, c1, c0, 2;		@ CPACR		\
+	mcr	p15, 0, r4, c2, c0, 2;		@ TTBCR		\
+	mcr	p15, 0, r5, c3, c0, 0;		@ DACR		\
+	mcrr	p15, 0, r6, r7, c2;		@ TTBR 0	\
+	mcrr	p15, 1, r8, r9, c2;		@ TTBR 1	\
+	mcr	p15, 0, r10, c10, c2, 0;	@ PRRR		\
+	mcr	p15, 0, r11, c10, c2, 1;	@ NMRR		\
+	mcr	p15, 2, r12, c0, c0, 0		@ CSSELR
+
+#define	store_cp15_regs_batch2					\
+	mcr	p15, 0, r2, c13, c0, 1;		@ CID		\
+	mcr	p15, 0, r3, c13, c0, 2;		@ TID_URW	\
+	mcr	p15, 0, r4, c13, c0, 3;		@ TID_URO	\
+	mcr	p15, 0, r5, c13, c0, 4;		@ TID_PRIV	\
+	mcr	p15, 0, r6, c5, c0, 0;		@ DFSR		\
+	mcr	p15, 0, r7, c5, c0, 1;		@ IFSR		\
+	mcr	p15, 0, r8, c5, c1, 0;		@ ADFSR		\
+	mcr	p15, 0, r9, c5, c1, 1;		@ AIFSR		\
+	mcr	p15, 0, r10, c6, c0, 0;		@ DFAR		\
+	mcr	p15, 0, r11, c6, c0, 2;		@ IFAR		\
+	mcr	p15, 0, r12, c12, c0, 0		@ VBAR
+
+#define	store_cp15_regs_batch3					\
+	mcr	p15, 0, r2, c14, c1, 0;		@ CNTKCTL	\
+	mcrr	p15, 0, r3, r4, c7;		@ PAR		\
+	mcr	p15, 0, r5, c10, c3, 0;		@ AMAIR0	\
+	mcr	p15, 0, r6, c10, c3, 1		@ AMAIR1
+
+#define	store_guest_cp15_regs_batch1				\
+	str	r2, [r0, #HYPCTX_CP15_SCTLR];			\
+	str	r3, [r0, #HYPCTX_CP15_CPACR];			\
+	str	r4, [r0, #HYPCTX_CP15_TTBCR];			\
+	str	r5, [r0, #HYPCTX_CP15_DACR];			\
+	add	r2, r0, #HYPCTX_CP15_TTBR0;			\
+	strd	r6, r7, [r2];					\
+	add	r2, r0, #HYPCTX_CP15_TTBR1;			\
+	strd	r8, r9, [r2];					\
+	str	r10, [r0, #HYPCTX_CP15_PRRR];			\
+	str	r11, [r0, #HYPCTX_CP15_NMRR];			\
+	str	r12, [r0, #HYPCTX_CP15_CSSELR]
+
+#define	store_guest_cp15_regs_batch2				\
+	str	r2, [r0, #HYPCTX_CP15_CID];			\
+	str	r3, [r0, #HYPCTX_CP15_TID_URW];			\
+	str	r4, [r0, #HYPCTX_CP15_TID_URO];			\
+	str	r5, [r0, #HYPCTX_CP15_TID_PRIV];		\
+	str	r6, [r0, #HYPCTX_CP15_DFSR];			\
+	str	r7, [r0, #HYPCTX_CP15_IFSR];			\
+	str	r8, [r0, #HYPCTX_CP15_ADFSR];			\
+	str	r9, [r0, #HYPCTX_CP15_AIFSR];			\
+	str	r10, [r0, #HYPCTX_CP15_DFAR];			\
+	str	r11, [r0, #HYPCTX_CP15_IFAR];			\
+	str	r12, [r0, #HYPCTX_CP15_VBAR]
+
+#define	store_guest_cp15_regs_batch3				\
+	str	r2, [r0, #HYPCTX_CP15_CNTKCTL];			\
+	add	r2, r0, #HYPCTX_CP15_PAR;			\
+	strd	r4, r5, [r2];					\
+	str	r3, [r0, #HYPCTX_CP15_AMAIR0];			\
+	str	r6, [r0, #HYPCTX_CP15_AMAIR1]
+
+#define	load_guest_cp15_regs_batch1				\
+	ldr	r2, [r0, #HYPCTX_CP15_SCTLR];			\
+	ldr	r3, [r0, #HYPCTX_CP15_CPACR];			\
+	ldr	r4, [r0, #HYPCTX_CP15_TTBCR];			\
+	ldr	r5, [r0, #HYPCTX_CP15_DACR];			\
+	add	r2, r0, #HYPCTX_CP15_TTBR0;			\
+	ldrd	r6, r7, [r2];					\
+	add	r2, r0, #HYPCTX_CP15_TTBR1;			\
+	ldrd	r8, r9, [r2];					\
+	ldr	r10, [r0, #HYPCTX_CP15_PRRR];			\
+	ldr	r11, [r0, #HYPCTX_CP15_NMRR];			\
+	ldr	r12, [r0, #HYPCTX_CP15_CSSELR]
+
+#define	load_guest_cp15_regs_batch2				\
+	ldr	r2, [r0, #HYPCTX_CP15_CID];			\
+	ldr	r3, [r0, #HYPCTX_CP15_TID_URW];			\
+	ldr	r4, [r0, #HYPCTX_CP15_TID_URO];			\
+	ldr	r5, [r0, #HYPCTX_CP15_TID_PRIV];		\
+	ldr	r6, [r0, #HYPCTX_CP15_DFSR];			\
+	ldr	r7, [r0, #HYPCTX_CP15_IFSR];			\
+	ldr	r8, [r0, #HYPCTX_CP15_ADFSR];			\
+	ldr	r9, [r0, #HYPCTX_CP15_AIFSR];			\
+	ldr	r10, [r0, #HYPCTX_CP15_DFAR];			\
+	ldr	r11, [r0, #HYPCTX_CP15_IFAR];			\
+	ldr	r12, [r0, #HYPCTX_CP15_VBAR]
+
+#define	load_guest_cp15_regs_batch3				\
+	ldr	r2, [r0, #HYPCTX_CP15_CNTKCTL];			\
+	add	r2, r0, #HYPCTX_CP15_PAR;			\
+	ldrd	r4, r5, [r2];					\
+	ldr	r3, [r0, #HYPCTX_CP15_AMAIR0];			\
+	ldr	r6, [r0, #HYPCTX_CP15_AMAIR1]
+
 #endif

Added: soc2015/mihai/bhyve-on-arm-head/sys/arm/vmm/hyp_genassym.c
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ soc2015/mihai/bhyve-on-arm-head/sys/arm/vmm/hyp_genassym.c	Tue Jun 30 15:02:00 2015	(r287759)
@@ -0,0 +1,94 @@
+#include <sys/cdefs.h>
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/proc.h>
+#include <sys/assym.h>
+
+#include <vm/vm.h>
+#include <vm/pmap.h>
+
+#include <machine/vmm.h>
+#include "arm.h"
+
+ASSYM(HYPCTX_HYP, offsetof(struct hypctx, hyp));
+ASSYM(HYP_VTTBR, offsetof(struct hyp, vttbr));
+
+ASSYM(HYPCTX_MIDR, offsetof(struct hypctx, midr));
+ASSYM(HYPCTX_MPIDR, offsetof(struct hypctx, mpidr));
+ASSYM(HYPCTX_HCR, offsetof(struct hypctx, hcr));
+
+ASSYM(HYPCTX_SP_und, offsetof(struct hypctx, sp_und));
+ASSYM(HYPCTX_LR_und, offsetof(struct hypctx, lr_und));
+ASSYM(HYPCTX_SPSR_und, offsetof(struct hypctx, spsr_und));
+ASSYM(HYPCTX_SP_svc, offsetof(struct hypctx, sp_svc));
+ASSYM(HYPCTX_LR_svc, offsetof(struct hypctx, lr_svc));
+ASSYM(HYPCTX_SPSR_svc, offsetof(struct hypctx, spsr_svc));
+ASSYM(HYPCTX_SP_abt, offsetof(struct hypctx, sp_abt));
+ASSYM(HYPCTX_LR_abt, offsetof(struct hypctx, lr_abt));
+ASSYM(HYPCTX_SPSR_abt, offsetof(struct hypctx, spsr_abt));
+ASSYM(HYPCTX_SP_irq, offsetof(struct hypctx, sp_irq));
+ASSYM(HYPCTX_LR_irq, offsetof(struct hypctx, lr_irq));
+ASSYM(HYPCTX_SPSR_irq, offsetof(struct hypctx, spsr_irq));
+ASSYM(HYPCTX_SP_fiq, offsetof(struct hypctx, sp_fiq));
+ASSYM(HYPCTX_LR_fiq, offsetof(struct hypctx, lr_fiq));
+ASSYM(HYPCTX_SPSR_fiq, offsetof(struct hypctx, spsr_fiq));
+ASSYM(HYPCTX_r8_fiq, offsetof(struct hypctx, r8_fiq));
+ASSYM(HYPCTX_r9_fiq, offsetof(struct hypctx, r9_fiq));
+ASSYM(HYPCTX_r10_fiq, offsetof(struct hypctx, r10_fiq));
+ASSYM(HYPCTX_r11_fiq, offsetof(struct hypctx, r11_fiq));
+ASSYM(HYPCTX_r12_fiq, offsetof(struct hypctx, r12_fiq));
+
+ASSYM(HYPCTX_REGS, offsetof(struct hypctx, regs));
+ASSYM(HYPCTX_REGS_LR, offsetof(struct hypctx, regs.r_lr));
+ASSYM(HYPCTX_REGS_SP, offsetof(struct hypctx, regs.r_sp));
+ASSYM(HYPCTX_REGS_PC, offsetof(struct hypctx, regs.r_pc));
+ASSYM(HYPCTX_REGS_CPSR, offsetof(struct hypctx, regs.r_cpsr));
+
+
+ASSYM(HYPCTX_CP15_SCTLR, offsetof(struct hypctx, cp15_sctlr));
+ASSYM(HYPCTX_CP15_CPACR, offsetof(struct hypctx, cp15_cpacr));
+ASSYM(HYPCTX_CP15_TTBCR, offsetof(struct hypctx, cp15_ttbcr));
+ASSYM(HYPCTX_CP15_DACR, offsetof(struct hypctx, cp15_dacr));
+ASSYM(HYPCTX_CP15_TTBR0, offsetof(struct hypctx, cp15_ttbr0));
+ASSYM(HYPCTX_CP15_TTBR1, offsetof(struct hypctx, cp15_ttbr1));
+ASSYM(HYPCTX_CP15_PRRR, offsetof(struct hypctx, cp15_prrr));
+ASSYM(HYPCTX_CP15_NMRR, offsetof(struct hypctx, cp15_nmrr));
+ASSYM(HYPCTX_CP15_CSSELR, offsetof(struct hypctx, cp15_csselr));
+ASSYM(HYPCTX_CP15_CID, offsetof(struct hypctx, cp15_cid));
+ASSYM(HYPCTX_CP15_TID_URW, offsetof(struct hypctx, cp15_tid_urw));
+ASSYM(HYPCTX_CP15_TID_URO, offsetof(struct hypctx, cp15_tid_uro));
+ASSYM(HYPCTX_CP15_TID_PRIV, offsetof(struct hypctx, cp15_tid_priv));
+ASSYM(HYPCTX_CP15_DFSR, offsetof(struct hypctx, cp15_dfsr));
+ASSYM(HYPCTX_CP15_IFSR, offsetof(struct hypctx, cp15_ifsr));
+ASSYM(HYPCTX_CP15_ADFSR, offsetof(struct hypctx, cp15_adfsr));
+ASSYM(HYPCTX_CP15_AIFSR, offsetof(struct hypctx, cp15_aifsr));
+ASSYM(HYPCTX_CP15_DFAR, offsetof(struct hypctx, cp15_dfar));
+ASSYM(HYPCTX_CP15_IFAR, offsetof(struct hypctx, cp15_ifar));
+ASSYM(HYPCTX_CP15_VBAR, offsetof(struct hypctx, cp15_vbar));
+ASSYM(HYPCTX_CP15_CNTKCTL, offsetof(struct hypctx, cp15_cntkctl));
+ASSYM(HYPCTX_CP15_PAR, offsetof(struct hypctx, cp15_par));
+ASSYM(HYPCTX_CP15_AMAIR0, offsetof(struct hypctx, cp15_amair0));
+ASSYM(HYPCTX_CP15_AMAIR1, offsetof(struct hypctx, cp15_amair1));
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+

Modified: soc2015/mihai/bhyve-on-arm-head/sys/modules/vmm-arm/Makefile
==============================================================================
--- soc2015/mihai/bhyve-on-arm-head/sys/modules/vmm-arm/Makefile	Tue Jun 30 14:17:02 2015	(r287758)
+++ soc2015/mihai/bhyve-on-arm-head/sys/modules/vmm-arm/Makefile	Tue Jun 30 15:02:00 2015	(r287759)
@@ -1,6 +1,8 @@
 KMOD=	vmm-arm
 
 SRCS=	opt_acpi.h opt_ddb.h device_if.h bus_if.h pci_if.h
+SRCS+=	hyp_assym.h
+DPSRCS=	hyp_genassym.c
 
 CFLAGS+= -DVMM_KEEP_STATS -DSMP
 CFLAGS+= -I${.CURDIR}/../../arm/vmm
@@ -14,5 +16,12 @@
 	arm.c		\
 	hyp.S
 
+CLEANFILES=	hyp_assym.h hyp_genassym.o
+
+hyp_assym.h:    hyp_genassym.o
+	sh ${SYSDIR}/kern/genassym.sh hyp_genassym.o > ${.TARGET}
+
+hyp_genassym.o:
+	${CC} -c ${CFLAGS:N-fno-common} ${.IMPSRC}
 
 .include <bsd.kmod.mk>



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