From owner-freebsd-current@freebsd.org Fri Aug 21 16:23:15 2015 Return-Path: Delivered-To: freebsd-current@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:1900:2254:206a::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id DD5E39BF9AC for ; Fri, 21 Aug 2015 16:23:15 +0000 (UTC) (envelope-from ian@freebsd.org) Received: from pmta2.delivery6.ore.mailhop.org (pmta2.delivery6.ore.mailhop.org [54.200.129.228]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mx1.freebsd.org (Postfix) with ESMTPS id BB43D62F for ; Fri, 21 Aug 2015 16:23:15 +0000 (UTC) (envelope-from ian@freebsd.org) Received: from ilsoft.org (unknown [73.34.117.227]) by outbound2.ore.mailhop.org (Halon Mail Gateway) with ESMTPSA; Fri, 21 Aug 2015 16:24:44 +0000 (UTC) Received: from rev (rev [172.22.42.240]) by ilsoft.org (8.14.9/8.14.9) with ESMTP id t7LGNDhA009208; Fri, 21 Aug 2015 10:23:13 -0600 (MDT) (envelope-from ian@freebsd.org) Message-ID: <1440174193.242.279.camel@freebsd.org> Subject: Re: freebsd-head: suddenly NMI panics lead to ddb being unable to stop CPUs? From: Ian Lepore To: Julian Elischer Cc: Adrian Chadd , freebsd-current Date: Fri, 21 Aug 2015 10:23:13 -0600 In-Reply-To: <55D74402.70104@freebsd.org> References: <55D74193.4020008@FreeBSD.org> <55D74402.70104@freebsd.org> Content-Type: text/plain; charset="us-ascii" X-Mailer: Evolution 3.12.10 FreeBSD GNOME Team Port Mime-Version: 1.0 Content-Transfer-Encoding: 7bit X-BeenThere: freebsd-current@freebsd.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: Discussions about the use of FreeBSD-current List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 21 Aug 2015 16:23:16 -0000 On Fri, 2015-08-21 at 23:30 +0800, Julian Elischer wrote: > On 8/21/15 11:25 PM, Adrian Chadd wrote: > > Ah, cool. I'll give it a whirl. > > > > I'm a little worried about having all of the other cores spinning in > > this case (mostly thermal; the machines get VERY LOUD when the CPUs > > are spinning..) > > > make each spin with the pause instruction.. and for N seconds (N being > the CPU ID) or something cpu_spinwait() is defined as ia32_pause() on i386 and amd64. The problem is that ONLY x86 arches benefit from cpu_spinwait(), it's just a nop on other arches, which turn into little radiant heaters for long spins (like while waiting for APs to be released). On ARM we have a really nice wait-for-event/signal-event pair of instructions, where WFE would be a natural for cpu_spinwait(), but would require a matching cpu_spinwake() type call to be sprinkled around to do the matching SEV instruction. -- Ian