Date: Sun, 8 Feb 2009 07:19:36 GMT From: Andrew Turner <andrew@FreeBSD.org> To: Perforce Change Reviews <perforce@freebsd.org> Subject: PERFORCE change 157355 for review Message-ID: <200902080719.n187Ja2P007436@repoman.freebsd.org>
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http://perforce.freebsd.org/chv.cgi?CH=157355 Change 157355 by andrew@andrew_bender on 2009/02/08 07:19:02 Move the definitions common to s3c2410 and s3c2440 to the common header and rename ass appropriate. Affected files ... .. //depot/projects/arm/src/sys/arm/s3c2xx0/neo1973_machdep.c#11 edit .. //depot/projects/arm/src/sys/arm/s3c2xx0/s3c2410reg.h#6 edit .. //depot/projects/arm/src/sys/arm/s3c2xx0/s3c24x0.c#3 edit .. //depot/projects/arm/src/sys/arm/s3c2xx0/s3c24x0_mci.c#5 edit .. //depot/projects/arm/src/sys/arm/s3c2xx0/s3c24x0_nand.c#4 edit .. //depot/projects/arm/src/sys/arm/s3c2xx0/s3c24x0reg.h#2 edit Differences ... ==== //depot/projects/arm/src/sys/arm/s3c2xx0/neo1973_machdep.c#11 (text+ko) ==== @@ -147,9 +147,9 @@ /* * Map the IRQ Controller */ - _A(S3C2410_INTCTL_BASE), - _A(S3C2410_INTCTL_BASE), - _S(S3C2410_INTCTL_SIZE), + _A(S3C24X0_INTCTL_BASE), + _A(S3C24X0_INTCTL_BASE), + _S(S3C24X0_INTCTL_SIZE), VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, }, @@ -157,9 +157,9 @@ /* * Map the UART to VA == PA */ - _A(S3C2410_UART0_BASE), - _A(S3C2410_UART0_BASE), - _S(S3C2410_UART_BASE(3) - S3C2410_UART0_BASE), + _A(S3C24X0_UART0_BASE), + _A(S3C24X0_UART0_BASE), + _S(S3C24X0_UART_BASE(3) - S3C24X0_UART0_BASE), VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, }, @@ -167,9 +167,9 @@ /* * Map the LCD to VA == PA */ - _A(S3C2410_LCDC_BASE), - _A(S3C2410_LCDC_BASE), - _S(S3C2410_LCDC_SIZE), + _A(S3C24X0_LCDC_BASE), + _A(S3C24X0_LCDC_BASE), + _S(S3C24X0_LCDC_SIZE), VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, }, @@ -177,8 +177,8 @@ /* * Map the MMC/SD to VA == PA */ - _A(S3C2410_SDI_BASE), - _A(S3C2410_SDI_BASE), + _A(S3C24X0_SDI_BASE), + _A(S3C24X0_SDI_BASE), _S(S3C2410_SDI_SIZE), VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, @@ -187,8 +187,8 @@ /* * Map the IIC to VA == PA */ - _A(S3C2410_IIC_BASE), - _A(S3C2410_IIC_BASE), + _A(S3C24X0_IIC_BASE), + _A(S3C24X0_IIC_BASE), _S(S3C24X0_IIC_SIZE), VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, @@ -374,8 +374,8 @@ cpu_idcache_wbinv_all(); /* Disable all peripheral interrupts */ - ioreg_write32(S3C2410_INTCTL_BASE + INTCTL_INTMSK, ~0); - s3c2410_uart_vaddr = S3C2410_UART0_BASE; + ioreg_write32(S3C24X0_INTCTL_BASE + INTCTL_INTMSK, ~0); + s3c2410_uart_vaddr = S3C24X0_UART_BASE(0); cninit(); /* Set stack for exception handlers */ ==== //depot/projects/arm/src/sys/arm/s3c2xx0/s3c2410reg.h#6 (text+ko) ==== @@ -39,9 +39,7 @@ #ifndef _ARM_S3C2XX0_S3C2410REG_H_ #define _ARM_S3C2XX0_S3C2410REG_H_ -/* common definitions for S3C2800, S3C2400 and S3C2410 */ -#include <arm/s3c2xx0/s3c2xx0reg.h> -/* common definitions for S3C2400 and S3C2410 */ +/* common definitions for S3C2410 and S3C2440 */ #include <arm/s3c2xx0/s3c24x0reg.h> /* @@ -51,100 +49,19 @@ #define S3C2410_BANK_START(n) (S3C2410_BANK_SIZE*(n)) #define S3C2410_SDRAM_START S3C2410_BANK_START(6) -/* - * Physical address of integrated peripherals - */ -#define S3C2410_MEMCTL_BASE 0x48000000 /* memory controller */ -#define S3C2410_USBHC_BASE 0x49000000 /* USB Host controller */ -#define S3C2410_INTCTL_BASE 0x4a000000 /* Interrupt controller */ -#define S3C2410_DMAC_BASE 0x4b000000 -#define S3C2410_DMAC_SIZE 0xe4 -#define S3C2410_CLKMAN_BASE 0x4c000000 /* clock & power management */ -#define S3C2410_LCDC_BASE 0x4d000000 /* LCD controller */ -#define S3C2410_LCDC_SIZE 0x60 -#define S3C2410_NANDFC_BASE 0x4e000000 /* NAND Flash controller */ -#define S3C2410_NANDFC_SIZE 0x18 -#define S3C2410_UART0_BASE 0x50000000 -#define S3C2410_UART_BASE(n) (S3C2410_UART0_BASE+0x4000*(n)) -#define S3C2410_TIMER_BASE 0x51000000 -#define S3C2410_USBDC_BASE 0x5200140 -#define S3C2410_USBDC_SIZE 0x130 -#define S3C2410_WDT_BASE 0x53000000 -#define S3C2410_IIC_BASE 0x54000000 -#define S3C2410_IIS_BASE 0x55000000 -#define S3C2410_GPIO_BASE 0x56000000 -#define S3C2410_GPIO_SIZE 0xb4 -#define S3C2410_ADC_BASE 0x58000000 -#define S3C2410_ADC_SIZE 0x14 -#define S3C2410_SPI0_BASE 0x59000000 -#define S3C2410_SPI1_BASE 0x59000020 -#define S3C2410_SDI_BASE 0x5a000000 /* SD Interface */ -#define S3C2410_SDI_SIZE 0x44 - -#define S3C2410_REG_BASE 0x48000000 -#define S3C2410_REG_SIZE 0x13000000 -/* interrupt control (additional defs for 2410) */ -#define ICU_LEN (32+11) - -#define INTCTL_SUBSRCPND 0x18 /* sub source pending (2410 only) */ -#define INTCTL_INTSUBMSK 0x1c /* sub mask (2410 only) */ - -/* 2410 has more than 32 interrupt sources. These are sub-sources - * that are OR-ed into main interrupt sources, and controlled via - * SUBSRCPND and SUBSRCMSK registers */ - -#define S3C2410_SUBIRQ_MIN 32 -#define S3C2410_SUBIRQ_MAX (32+10) - -/* cascaded to INT_ADCTC */ -#define S3C2410_INT_ADC (S3C2410_SUBIRQ_MIN+10) /* AD converter */ -#define S3C2410_INT_TC (S3C2410_SUBIRQ_MIN+9) /* Touch screen */ -/* cascaded to INT_UART2 */ -#define S3C2410_INT_ERR2 (S3C2410_SUBIRQ_MIN+8) /* UART2 Error interrupt */ -#define S3C2410_INT_TXD2 (S3C2410_SUBIRQ_MIN+7) /* UART2 Tx interrupt */ -#define S3C2410_INT_RXD2 (S3C2410_SUBIRQ_MIN+6) /* UART2 Rx interrupt */ -/* cascaded to INT_UART1 */ -#define S3C2410_INT_ERR1 (S3C2410_SUBIRQ_MIN+5) /* UART1 Error interrupt */ -#define S3C2410_INT_TXD1 (S3C2410_SUBIRQ_MIN+4) /* UART1 Tx interrupt */ -#define S3C2410_INT_RXD1 (S3C2410_SUBIRQ_MIN+3) /* UART1 Rx interrupt */ -/* cascaded to INT_UART0 */ -#define S3C2410_INT_ERR0 (S3C2410_SUBIRQ_MIN+2) /* UART0 Error interrupt */ -#define S3C2410_INT_TXD0 (S3C2410_SUBIRQ_MIN+1) /* UART0 Tx interrupt */ -#define S3C2410_INT_RXD0 (S3C2410_SUBIRQ_MIN+0) /* UART0 Rx interrupt */ - -#define S3C2410_INTCTL_SIZE 0x20 +/* interrupt control */ +#define S3C2410_SUBIRQ_MAX (S3C24X0_SUBIRQ_MIN+10) - /* Clock control */ -#define CLKMAN_LOCKTIME 0x00 -#define CLKMAN_MPLLCON 0x04 -#define CLKMAN_UPLLCON 0x08 -#define CLKMAN_CLKCON 0x0c -#define CLKCON_SPI (1<<18) -#define CLKCON_IIS (1<<17) -#define CLKCON_IIC (1<<16) -#define CLKCON_ADC (1<<15) -#define CLKCON_RTC (1<<14) -#define CLKCON_GPIO (1<<13) -#define CLKCON_UART2 (1<<12) -#define CLKCON_UART1 (1<<11) -#define CLKCON_UART0 (1<<10) /* PCLK to UART0 */ -#define CLKCON_SDI (1<<9) -#define CLKCON_TIMER (1<<8) /* PCLK to TIMER */ -#define CLKCON_USBD (1<<7) /* PCLK to USB device controller */ -#define CLKCON_USBH (1<<6) /* PCLK to USB host controller */ -#define CLKCON_LCDC (1<<5) /* PCLK to LCD controller */ -#define CLKCON_NANDFC (1<<4) /* PCLK to NAND Flash controller */ -#define CLKCON_IDLE (1<<2) /* 1=transition to IDLE mode */ +/* CLKMAN_CLKCON */ #define CLKCON_STOP (1<<0) /* 1=transition to STOP mode */ -#define CLKMAN_CLKSLOW 0x10 -#define CLKMAN_CLKDIVN 0x14 +/* CLKMAN_CLKDIVN */ #define CLKDIVN_HDIVN (1<<1) /* hclk=fclk/2 */ -#define CLKDIVN_PDIVN (1<<0) /* pclk=hclk/2 */ /* NAND Flash controller */ -#define NANDFC_NFCONF 0x00 /* Configuration */ +#define S3C2410_NANDFC_SIZE 0x18 +/* NANDFC_NFCONF */ #define NFCONF_ENABLE (1<<15) /* NAND controller enabled */ #define NFCONF_ECC (1<<12) /* Initialize ECC decoder/encoder */ #define NFCONF_FCE (1<<11) /* Flash chip enabled */ @@ -155,127 +72,18 @@ #define NANDFC_NFADDR 0x08 /* address */ #define NANDFC_NFDATA 0x0c /* data */ #define NANDFC_NFSTAT 0x10 /* operation status */ -#define NFSTAT_READY (1<<0) /* NAND flash memory ready/busy status */ #define NANDFC_NFECC 0x14 /* ecc */ /* GPIO */ -#define GPIO_PACON 0x00 /* port A configuration */ -#define PCON_INPUT 0 /* Input port */ -#define PCON_OUTPUT 1 /* Output port */ -#define PCON_ALTFUN 2 /* Alternate function */ -#define PCON_ALTFUN2 3 /* Alternate function */ -#define GPIO_PADAT 0x04 /* port A data */ -#define GPIO_PBCON 0x10 -#define GPIO_PBDAT 0x14 -#define GPIO_PBUP 0x18 -#define GPIO_PCCON 0x20 -#define GPIO_PCDAT 0x24 -#define GPIO_PCUP 0x28 -#define GPIO_PDCON 0x30 -#define GPIO_PDDAT 0x34 -#define GPIO_PDUP 0x38 -#define GPIO_PECON 0x40 -#define GPIO_PEDAT 0x44 -#define GPIO_PEUP 0x48 -#define GPIO_PFCON 0x50 -#define GPIO_PFDAT 0x54 -#define GPIO_PFUP 0x58 -#define GPIO_PGCON 0x60 -#define GPIO_PGDAT 0x64 -#define GPIO_PGUP 0x68 -#define GPIO_PHCON 0x70 -#define GPIO_PHDAT 0x74 -#define GPIO_PHUP 0x78 -#define GPIO_MISCCR 0x80 /* miscellaneous control */ -#define GPIO_DCLKCON 0x84 /* DCLK 0/1 */ -#define GPIO_EXTINT(n) (0x88+4*(n)) /* external int control 0/1/2 */ -#define GPIO_EINTFLT(n) (0x94+4*(n)) /* external int filter control 0..3 */ -#define GPIO_EINTMASK 0xa4 -#define GPIO_EINTPEND 0xa8 -#define GPIO_GSTATUS0 0xac /* external pin status */ -#define GPIO_GSTATUS1 0xb0 /* external pin status */ - -#define GPIO_SET_FUNC(v,port,func) \ - (((v) & ~(3<<(2*(port))))|((func)<<(2*(port)))) - -#define EXTINTR_LOW 0x00 -#define EXTINTR_HIGH 0x01 -#define EXTINTR_FALLING 0x02 -#define EXTINTR_RISING 0x04 -#define EXTINTR_BOTH 0x06 +#define S3C2410_GPIO_SIZE 0xb4 /* SD interface */ -#define SDI_CON 0x00 -#define SDI_PRE 0x04 -#define SDI_CARG 0x08 -#define SDI_CCON 0x0c -#define CCON_ABORDCMD (1<<12) /* Abort SDIO CMD12/52 */ -#define CCON_WITHDATA (1<<11) /* CMD with data */ -#define CCON_LONGRSP (1<<10) /* 136 bit response */ -#define CCON_WAITRSP (1<<9) /* Host waits for response */ -#define CCON_CMD_START (1<<8) -#define CCON_CMDINDEX_MASK (0x7F) /* Command number index */ -#define SDI_CSTA 0x10 -#define CSTA_RSPFAIL (1<<12) -#define CSTA_CMDSENT (1<<11) -#define CSTA_CMDTOUT (1<<10) -#define CSTA_RSPFIN (1<<9) -#define CSTA_CMDON (1<<8) -#define SDI_RSP0 0x14 -#define SDI_RSP1 0x18 -#define SDI_RSP2 0x1c -#define SDI_RSP3 0x20 -#define SDI_DTIMER 0x24 -#define SDI_BSIZE 0x28 -#define SDI_DCON 0x2c -#define DCON_PRDTYPE (1<<21) -#define DCON_TARSP (1<<20) /* Transmit after response */ -#define DCON_RACMD (1<<19) /* Receive after command */ -#define DCON_BACMD (1<<18) /* Busy after command */ -#define DCON_BLKMODE (1<<17) /* Stream/Block mode */ -#define DCON_WIDEBUS (1<<16) /* Standard/Wide bus */ -#define DCON_ENDMA (1<<15) /* DMA Enable */ +#define S3C2410_SDI_SIZE 0x44 #define DCON_STOP (1<<14) /* Force the transfer to stop */ -/* Determine the direction of the data transfer */ -#define DCON_DATA_READY (0<<12) /* No transfer */ -#define DCON_ONLYBUST (1<<12) /* Check if busy */ -#define DCON_DATA_RECEIVE (2<<12) /* Receive data from SD */ -#define DCON_DATA_TRANSMIT (3<<12) /* Send data to SD */ -#define DCON_BLKNUM_MASK (0x7FF) /* Block number */ -#define SDI_DCNT 0x30 -#define SDI_DSTA 0x34 -#define SDI_FSTA 0x38 -#define SDI_DAT 0x3c -#define SDI_IMSK 0x40 /* Interrupt mask */ +#define S3C2410_SDI_DAT 0x3c +#define S3C2410_SDI_IMSK 0x40 /* Interrupt mask */ /* ADC */ -/* XXX: ADCCON register is common to both S3C2410 and S3C2400, - * but other registers are different. - */ -#define ADC_ADCCON 0x00 -#define ADCCON_ENABLE_START (1<<0) -#define ADCCON_READ_START (1<<1) -#define ADCCON_STDBM (1<<2) -#define ADCCON_SEL_MUX_SHIFT 3 -#define ADCCON_SEL_MUX_MASK (0x7<<ADCCON_SEL_MUX_SHIFT) -#define ADCCON_PRSCVL_SHIFT 6 -#define ADCCON_PRSCVL_MASK (0xff<<ADCCON_PRSCVL_SHIFT) -#define ADCCON_PRSCEN (1<<14) -#define ADCCON_ECFLG (1<<15) - -#define ADC_ADCTSC 0x04 -#define ADCTSC_XY_PST 0x03 -#define ADCTSC_AUTO_PST (1<<2) -#define ADCTSC_PULL_UP (1<<3) -#define ADCTSC_XP_SEN (1<<4) -#define ADCTSC_XM_SEN (1<<5) -#define ADCTSC_YP_SEN (1<<6) -#define ADCTSC_YM_SEN (1<<7) -#define ADCTSC_UD_SEN (1<<8) -#define ADC_ADCDLY 0x08 -#define ADC_ADCDAT0 0x0c -#define ADC_ADCDAT1 0x10 - -#define ADCDAT_DATAMASK 0x3ff +#define S3C2410_ADC_SIZE 0x14 #endif /* _ARM_S3C2XX0_S3C2410REG_H_ */ ==== //depot/projects/arm/src/sys/arm/s3c2xx0/s3c24x0.c#3 (text+ko) ==== @@ -46,7 +46,7 @@ #include <machine/cpufunc.h> #include <machine/intr.h> #include <arm/s3c2xx0/s3c2410reg.h> -#include <arm/s3c2xx0/s3c2410var.h> +#include <arm/s3c2xx0/s3c24x0var.h> #include <sys/rman.h> #define S3C2XX0_XTAL_CLK 12000000 @@ -190,20 +190,20 @@ if (type == SYS_RES_IRQ && start == end) { switch (start) { case S3C24X0_INT_ADCTC: - start = S3C2410_INT_TC; - end = S3C2410_INT_ADC; + start = S3C24X0_INT_TC; + end = S3C24X0_INT_ADC; break; - case S3C2410_INT_UART0: - start = S3C2410_INT_RXD0; - end = S3C2410_INT_ERR0; + case S3C24X0_INT_UART0: + start = S3C24X0_INT_RXD0; + end = S3C24X0_INT_ERR0; break; - case S3C2410_INT_UART1: - start = S3C2410_INT_RXD1; - end = S3C2410_INT_ERR1; + case S3C24X0_INT_UART1: + start = S3C24X0_INT_RXD1; + end = S3C24X0_INT_ERR1; break; - case S3C2410_INT_UART2: - start = S3C2410_INT_RXD2; - end = S3C2410_INT_ERR2; + case S3C24X0_INT_UART2: + start = S3C24X0_INT_RXD2; + end = S3C24X0_INT_ERR2; break; default: break; @@ -304,43 +304,43 @@ sc->sc_sx.sc_iot = iot = &s3c2xx0_bs_tag; if (bus_space_map(iot, - S3C2410_INTCTL_BASE, S3C2410_INTCTL_SIZE, + S3C24X0_INTCTL_BASE, S3C24X0_INTCTL_SIZE, BUS_SPACE_MAP_LINEAR, &sc->sc_sx.sc_intctl_ioh)) panic("Cannot map registers"); /* Map the GPIO registers */ - if (bus_space_map(iot, S3C2410_GPIO_BASE, S3C2410_GPIO_SIZE, + if (bus_space_map(iot, S3C24X0_GPIO_BASE, S3C2410_GPIO_SIZE, 0, &sc->sc_sx.sc_gpio_ioh)) panic("Cannot map GPIO registers"); /* Memory controller */ - if (bus_space_map(iot, S3C2410_MEMCTL_BASE, + if (bus_space_map(iot, S3C24X0_MEMCTL_BASE, S3C24X0_MEMCTL_SIZE, 0, &sc->sc_sx.sc_memctl_ioh)) panic("cannot map MEMC"); /* Clock manager */ - if (bus_space_map(iot, S3C2410_CLKMAN_BASE, + if (bus_space_map(iot, S3C24X0_CLKMAN_BASE, S3C24X0_CLKMAN_SIZE, 0, &sc->sc_sx.sc_clkman_ioh)) panic("cannot map clock"); /* LCD controller */ - if (bus_space_map(iot, S3C2410_LCDC_BASE, - S3C2410_LCDC_SIZE, 0, &sc->sc_sx.sc_lcd_ioh)) + if (bus_space_map(iot, S3C24X0_LCDC_BASE, + S3C24X0_LCDC_SIZE, 0, &sc->sc_sx.sc_lcd_ioh)) panic("cannot map LCD"); /* MMC/SD */ - if (bus_space_map(iot, S3C2410_SDI_BASE, + if (bus_space_map(iot, S3C24X0_SDI_BASE, S3C2410_SDI_SIZE, 0, &sc->sc_sx.sc_mci_ioh)) panic("cannot map MMC/SD"); /* I2C */ - if (bus_space_map(iot, S3C2410_IIC_BASE, + if (bus_space_map(iot, S3C24X0_IIC_BASE, S3C24X0_IIC_SIZE, 0, &sc->sc_sx.sc_iic_ioh)) panic("cannot map IIC"); #if 0 /* Real time clock */ - if (bus_space_map(iot, S3C2410_RTC_BASE, + if (bus_space_map(iot, S3C24X0_RTC_BASE, S3C24X0_RTC_SIZE, 0, &sc->sc_sx.sc_rtc_ioh)) FAIL("RTC"); #endif - if (bus_space_map(iot, S3C2410_TIMER_BASE, + if (bus_space_map(iot, S3C24X0_TIMER_BASE, S3C24X0_TIMER_SIZE, 0, &sc->sc_timer_ioh)) panic("cannot map TIMER"); @@ -360,33 +360,33 @@ * Attach children devices */ s3c2xx0_softc->s3c2xx0_irq_rman.rm_type = RMAN_ARRAY; - s3c2xx0_softc->s3c2xx0_irq_rman.rm_descr = "S3C2410 IRQs"; + s3c2xx0_softc->s3c2xx0_irq_rman.rm_descr = "S3C24X0 IRQs"; s3c2xx0_softc->s3c2xx0_mem_rman.rm_type = RMAN_ARRAY; - s3c2xx0_softc->s3c2xx0_mem_rman.rm_descr = "S3C2410 Memory"; + s3c2xx0_softc->s3c2xx0_mem_rman.rm_descr = "S3C24X0 Memory"; if (rman_init(&s3c2xx0_softc->s3c2xx0_irq_rman) != 0 || rman_manage_region(&s3c2xx0_softc->s3c2xx0_irq_rman, 0, - S3C2410_SUBIRQ_MAX - 1) != 0) - panic("s3c2410_attach: failed to set up IRQ rman"); + S3C2410_SUBIRQ_MAX) != 0) + panic("s3c24x0_attach: failed to set up IRQ rman"); /* Manage the registor memory space */ if (rman_init(&s3c2xx0_softc->s3c2xx0_mem_rman) != 0 || - rman_manage_region(&s3c2xx0_softc->s3c2xx0_mem_rman, S3C2410_REG_BASE, - S3C2410_REG_BASE + S3C2410_REG_SIZE) != 0) - panic("s3c2410_attach: failed to set up register rman"); + rman_manage_region(&s3c2xx0_softc->s3c2xx0_mem_rman, S3C24X0_REG_BASE, + S3C24X0_REG_BASE + S3C24X0_REG_SIZE) != 0) + panic("s3c24x0_attach: failed to set up register rman"); s3c24x0_add_child(dev, 0, "nand", 0); s3c24x0_add_child(dev, 0, "timer", 0); /* Add the MMC/SD and set it's irq/registers */ child = s3c24x0_add_child(dev, 0, "s3c24x0_mci", 0); - bus_set_resource(child, SYS_RES_IRQ, 0, S3C2410_INT_SDI, 1); - bus_set_resource(child, SYS_RES_IOPORT, 0, S3C2410_SDI_BASE, + bus_set_resource(child, SYS_RES_IRQ, 0, S3C24X0_INT_SDI, 1); + bus_set_resource(child, SYS_RES_IOPORT, 0, S3C24X0_SDI_BASE, S3C2410_SDI_SIZE); /* Add the uart and set it's irq and registers */ child = s3c24x0_add_child(dev, 0, "uart", 0); - bus_set_resource(child, SYS_RES_IRQ, 0, S3C2410_INT_UART0, 1); - bus_set_resource(child, SYS_RES_IOPORT, 0, S3C2410_UART0_BASE, - S3C2410_UART_BASE(1) - S3C2410_UART0_BASE); + bus_set_resource(child, SYS_RES_IRQ, 0, S3C24X0_INT_UART0, 1); + bus_set_resource(child, SYS_RES_IOPORT, 0, S3C24X0_UART0_BASE, + S3C24X0_UART_BASE(1) - S3C24X0_UART0_BASE); bus_generic_probe(dev); bus_generic_attach(dev); @@ -465,7 +465,7 @@ { (void) disable_interrupts(I32_bit|F32_bit); - *(volatile unsigned int *)(S3C2410_WDT_BASE + WDT_WTCON) + *(volatile unsigned int *)(S3C24X0_WDT_BASE + WDT_WTCON) = (0 << WTCON_PRESCALE_SHIFT) | WTCON_ENABLE | WTCON_CLKSEL_16 | WTCON_ENRST; for(;;); @@ -497,9 +497,9 @@ switch (irq) { case S3C24X0_INT_ADCTC: - case S3C2410_INT_UART0: - case S3C2410_INT_UART1: - case S3C2410_INT_UART2: + case S3C24X0_INT_UART0: + case S3C24X0_INT_UART1: + case S3C24X0_INT_UART2: /* Find the sub IRQ */ irq = 0x7ff; irq &= bus_space_read_4(&s3c2xx0_bs_tag, @@ -516,7 +516,7 @@ s3c2xx0_softc->sc_intctl_ioh, INTCTL_SUBSRCPND, (1 << irq)); - return (S3C2410_SUBIRQ_MIN + irq); + return (S3C24X0_SUBIRQ_MIN + irq); } return (irq); @@ -529,7 +529,7 @@ { u_int32_t mask; - if (irq < S3C2410_SUBIRQ_MIN) { + if (irq < S3C24X0_SUBIRQ_MIN) { mask = bus_space_read_4(&s3c2xx0_bs_tag, s3c2xx0_softc->sc_intctl_ioh, INTCTL_INTMSK); mask |= (1 << irq); @@ -538,7 +538,7 @@ } else { mask = bus_space_read_4(&s3c2xx0_bs_tag, s3c2xx0_softc->sc_intctl_ioh, INTCTL_INTSUBMSK); - mask |= (1 << (irq - S3C2410_SUBIRQ_MIN)); + mask |= (1 << (irq - S3C24X0_SUBIRQ_MIN)); bus_space_write_4(&s3c2xx0_bs_tag, s3c2xx0_softc->sc_intctl_ioh, INTCTL_INTSUBMSK, mask); } @@ -549,35 +549,35 @@ { u_int32_t mask; - if (irq >= S3C2410_SUBIRQ_MIN) { + if (irq >= S3C24X0_SUBIRQ_MIN) { mask = bus_space_read_4(&s3c2xx0_bs_tag, s3c2xx0_softc->sc_intctl_ioh, INTCTL_INTSUBMSK); - mask &= ~(1 << (irq - S3C2410_SUBIRQ_MIN)); + mask &= ~(1 << (irq - S3C24X0_SUBIRQ_MIN)); bus_space_write_4(&s3c2xx0_bs_tag, s3c2xx0_softc->sc_intctl_ioh, INTCTL_INTSUBMSK, mask); /* Find the other irq to unmask */ switch (irq) { - case S3C2410_INT_ADC: - case S3C2410_INT_TC: + case S3C24X0_INT_ADC: + case S3C24X0_INT_TC: irq = S3C24X0_INT_ADCTC; break; - case S3C2410_INT_RXD0: - case S3C2410_INT_TXD0: - case S3C2410_INT_ERR0: - irq = S3C2410_INT_UART0; + case S3C24X0_INT_RXD0: + case S3C24X0_INT_TXD0: + case S3C24X0_INT_ERR0: + irq = S3C24X0_INT_UART0; break; - case S3C2410_INT_RXD1: - case S3C2410_INT_TXD1: - case S3C2410_INT_ERR1: - irq = S3C2410_INT_UART1; + case S3C24X0_INT_RXD1: + case S3C24X0_INT_TXD1: + case S3C24X0_INT_ERR1: + irq = S3C24X0_INT_UART1; break; - case S3C2410_INT_RXD2: - case S3C2410_INT_TXD2: - case S3C2410_INT_ERR2: - irq = S3C2410_INT_UART2; + case S3C24X0_INT_RXD2: + case S3C24X0_INT_TXD2: + case S3C24X0_INT_ERR2: + irq = S3C24X0_INT_UART2; break; default: /* We don't know which other IRQ to unmask */ ==== //depot/projects/arm/src/sys/arm/s3c2xx0/s3c24x0_mci.c#5 (text+ko) ==== @@ -286,7 +286,7 @@ vaddr = cmd->data->data; write_cnt = cmd->data->len; while (write_cnt > 0) { - WR4(sc, SDI_DAT, *(vaddr++)); + WR4(sc, S3C2410_SDI_DAT, *(vaddr++)); write_cnt -= 4; } } @@ -294,7 +294,7 @@ vaddr = cmd->data->data; read_cnt = cmd->data->len; while (read_cnt > 0) { - *(vaddr++) = RD4(sc, SDI_DAT); + *(vaddr++) = RD4(sc, S3C2410_SDI_DAT); read_cnt -= 4; } } ==== //depot/projects/arm/src/sys/arm/s3c2xx0/s3c24x0_nand.c#4 (text+ko) ==== @@ -131,7 +131,7 @@ sc->sc_sx.sc_iot = iot = &s3c2xx0_bs_tag; - if (bus_space_map(sc->sc_sx.sc_iot, S3C2410_NANDFC_BASE, + if (bus_space_map(sc->sc_sx.sc_iot, S3C24X0_NANDFC_BASE, S3C2410_NANDFC_SIZE, 0, &sc->sc_nand_ioh)) panic("Cannot map NAND registers"); ==== //depot/projects/arm/src/sys/arm/s3c2xx0/s3c24x0reg.h#2 (text+ko) ==== @@ -40,6 +40,39 @@ #ifndef _ARM_S3C2XX0_S3C24X0REG_H_ #define _ARM_S3C2XX0_S3C24X0REG_H_ +/* common definitions for S3C2800, S3C2410 and S3C2440 */ +#include <arm/s3c2xx0/s3c2xx0reg.h> + +/* + * Physical address of integrated peripherals + */ +#define S3C24X0_MEMCTL_BASE 0x48000000 /* memory controller */ +#define S3C24X0_USBHC_BASE 0x49000000 /* USB Host controller */ +#define S3C24X0_INTCTL_BASE 0x4a000000 /* Interrupt controller */ +#define S3C24X0_INTCTL_SIZE 0x20 +#define S3C24X0_DMAC_BASE 0x4b000000 +#define S3C24X0_DMAC_SIZE 0xe4 +#define S3C24X0_CLKMAN_BASE 0x4c000000 /* clock & power management */ +#define S3C24X0_LCDC_BASE 0x4d000000 /* LCD controller */ +#define S3C24X0_LCDC_SIZE 0x64 +#define S3C24X0_NANDFC_BASE 0x4e000000 /* NAND Flash controller */ +#define S3C24X0_UART0_BASE 0x50000000 +#define S3C24X0_UART_BASE(n) (S3C24X0_UART0_BASE+0x4000*(n)) +#define S3C24X0_TIMER_BASE 0x51000000 +#define S3C24X0_USBDC_BASE 0x5200140 +#define S3C24X0_USBDC_SIZE 0x130 +#define S3C24X0_WDT_BASE 0x53000000 +#define S3C24X0_IIC_BASE 0x54000000 +#define S3C24X0_IIS_BASE 0x55000000 +#define S3C24X0_GPIO_BASE 0x56000000 +#define S3C24X0_ADC_BASE 0x58000000 +#define S3C24X0_SPI0_BASE 0x59000000 +#define S3C24X0_SPI1_BASE 0x59000020 +#define S3C24X0_SDI_BASE 0x5a000000 /* SD Interface */ + +#define S3C24X0_REG_BASE 0x48000000 +#define S3C24X0_REG_SIZE 0x13000000 + /* Memory controller */ #define MEMCTL_BWSCON 0x00 /* Bus width and wait status */ #define BWSCON_DW0_SHIFT 1 /* bank0 is odd */ @@ -101,31 +134,27 @@ #define INTCTL_PRIORITY 0x0c /* IRQ Priority control */ #define INTCTL_INTPND 0x10 /* Interrupt request status */ #define INTCTL_INTOFFSET 0x14 /* Interrupt request source */ +#define INTCTL_SUBSRCPND 0x18 /* sub source pending */ +#define INTCTL_INTSUBMSK 0x1c /* sub mask */ /* Interrupt source */ -#define S3C24X0_INT_ADCTC 31 /* ADC (and TC for 2410 */ +#define S3C24X0_INT_ADCTC 31 /* ADC (and TC for 2410) */ #define S3C24X0_INT_RTC 30 /* RTC alarm */ -#define S3C2400_INT_UTXD1 29 /* UART1 Tx INT (2400 only) */ -#define S3C2410_INT_SPI1 29 /* SPI 1 (2410 only) */ -#define S3C2400_INT_UTXD0 28 /* UART0 Tx INT (2400 only) */ -#define S3C2410_INT_UART0 28 /* UART0 (2410 only) */ +#define S3C24X0_INT_SPI1 29 /* SPI 1 */ +#define S3C24X0_INT_UART0 28 /* UART0 */ #define S3C24X0_INT_IIC 27 #define S3C24X0_INT_USBH 26 /* USB Host */ #define S3C24X0_INT_USBD 25 /* USB Device */ -#define S3C2400_INT_URXD1 24 /* UART1 Rx INT (2400 only) */ -#define S3C2400_INT_URXD0 23 /* UART0 Rx INT (2400 only) */ -#define S3C2410_INT_UART1 23 /* UART0 (2410 only) */ +#define S3C24X0_INT_UART1 23 /* UART0 (2410 only) */ #define S3C24X0_INT_SPI0 22 /* SPI 0 */ -#define S3C2400_INT_MMC 21 -#define S3C2410_INT_SDI 21 +#define S3C24X0_INT_SDI 21 #define S3C24X0_INT_DMA3 20 #define S3C24X0_INT_DMA2 19 #define S3C24X0_INT_DMA1 18 #define S3C24X0_INT_DMA0 17 -#define S3C2410_INT_LCD 16 +#define S3C24X0_INT_LCD 16 -#define S3C2400_INT_UERR 15 /* UART 0/1 Error int (2400) */ -#define S3C2410_INT_UART2 15 /* UART2 int (2410) */ +#define S3C24X0_INT_UART2 15 /* UART2 int (2410) */ #define S3C24X0_INT_TIMER4 14 #define S3C24X0_INT_TIMER3 13 #define S3C24X0_INT_TIMER2 12 @@ -134,11 +163,32 @@ #define S3C24X0_INT_TIMER(n) (10+(n)) /* timer interrupt [4:0] */ #define S3C24X0_INT_WDT 9 /* Watch dog timer */ #define S3C24X0_INT_TICK 8 -#define S3C2410_INT_BFLT 7 /* Battery fault */ -#define S3C2410_INT_8_23 5 /* Ext int 8..23 */ -#define S3C2410_INT_4_7 4 /* Ext int 4..7 */ -#define S3C24X0_INT_EXT(n) (n) /* External interrupt [7:0] for 2400, - * [3:0] for 2410 */ +#define S3C24X0_INT_BFLT 7 /* Battery fault */ +#define S3C24X0_INT_8_23 5 /* Ext int 8..23 */ +#define S3C24X0_INT_4_7 4 /* Ext int 4..7 */ +#define S3C24X0_INT_EXT(n) (n) /* External interrupt [3:0] for 24{1,4}0 */ + +/* 24{1,4}0 has more than 32 interrupt sources. These are sub-sources + * that are OR-ed into main interrupt sources, and controlled via + * SUBSRCPND and SUBSRCMSK registers */ +#define S3C24X0_SUBIRQ_MIN 32 + +/* cascaded to INT_ADCTC */ +#define S3C24X0_INT_ADC (S3C24X0_SUBIRQ_MIN+10) /* AD converter */ +#define S3C24X0_INT_TC (S3C24X0_SUBIRQ_MIN+9) /* Touch screen */ +/* cascaded to INT_UART2 */ +#define S3C24X0_INT_ERR2 (S3C24X0_SUBIRQ_MIN+8) /* UART2 Error interrupt */ +#define S3C24X0_INT_TXD2 (S3C24X0_SUBIRQ_MIN+7) /* UART2 Tx interrupt */ +#define S3C24X0_INT_RXD2 (S3C24X0_SUBIRQ_MIN+6) /* UART2 Rx interrupt */ +/* cascaded to INT_UART1 */ +#define S3C24X0_INT_ERR1 (S3C24X0_SUBIRQ_MIN+5) /* UART1 Error interrupt */ +#define S3C24X0_INT_TXD1 (S3C24X0_SUBIRQ_MIN+4) /* UART1 Tx interrupt */ +#define S3C24X0_INT_RXD1 (S3C24X0_SUBIRQ_MIN+3) /* UART1 Rx interrupt */ +/* cascaded to INT_UART0 */ +#define S3C24X0_INT_ERR0 (S3C24X0_SUBIRQ_MIN+2) /* UART0 Error interrupt */ +#define S3C24X0_INT_TXD0 (S3C24X0_SUBIRQ_MIN+1) /* UART0 Tx interrupt */ +#define S3C24X0_INT_RXD0 (S3C24X0_SUBIRQ_MIN+0) /* UART0 Rx interrupt */ + /* DMA controller */ /* XXX */ @@ -153,6 +203,25 @@ #define PLLCON_SDIV_SHIFT 0 #define PLLCON_SDIV_MASK (0x03<<PLLCON_SDIV_SHIFT) #define CLKMAN_CLKCON 0x0c +#define CLKCON_SPI (1<<18) +#define CLKCON_IIS (1<<17) +#define CLKCON_IIC (1<<16) +#define CLKCON_ADC (1<<15) +#define CLKCON_RTC (1<<14) +#define CLKCON_GPIO (1<<13) +#define CLKCON_UART2 (1<<12) +#define CLKCON_UART1 (1<<11) +#define CLKCON_UART0 (1<<10) /* PCLK to UART0 */ +#define CLKCON_SDI (1<<9) +#define CLKCON_TIMER (1<<8) /* PCLK to TIMER */ +#define CLKCON_USBD (1<<7) /* PCLK to USB device controller */ +#define CLKCON_USBH (1<<6) /* PCLK to USB host controller */ +#define CLKCON_LCDC (1<<5) /* PCLK to LCD controller */ +#define CLKCON_NANDFC (1<<4) /* PCLK to NAND Flash controller */ +#define CLKCON_IDLE (1<<2) /* 1=transition to IDLE mode */ +#define CLKMAN_CLKSLOW 0x10 +#define CLKMAN_CLKDIVN 0x14 +#define CLKDIVN_PDIVN (1<<0) /* pclk=hclk/2 */ #define CLKMAN_CLKSLOW 0x10 /* slow clock controll */ #define CLKSLOW_UCLK (1<<7) /* 1=UPLL off */ @@ -304,6 +373,57 @@ #define S3C24X0_LCDC_SIZE (LCDC_PALETTE+LCDC_PALETTE_SIZE) +/* NAND Flash controller */ +#define NANDFC_NFCONF 0x00 /* Configuration */ +/* NANDFC_NFSTAT */ +#define NFSTAT_READY (1<<0) /* NAND flash memory ready/busy status */ + +/* XXX: Move to s3c2440reg.h */ +#define S3C2440_NANDFC_SIZE 0x40 + + +/* MMC/SD */ +#define SDI_CON 0x00 +#define SDI_PRE 0x04 +#define SDI_CARG 0x08 +#define SDI_CCON 0x0c +#define CCON_ABORDCMD (1<<12) /* Abort SDIO CMD12/52 */ +#define CCON_WITHDATA (1<<11) /* CMD with data */ +#define CCON_LONGRSP (1<<10) /* 136 bit response */ +#define CCON_WAITRSP (1<<9) /* Host waits for response */ +#define CCON_CMD_START (1<<8) +#define CCON_CMDINDEX_MASK (0x7F) /* Command number index */ +#define SDI_CSTA 0x10 +#define CSTA_RSPFAIL (1<<12) +#define CSTA_CMDSENT (1<<11) +#define CSTA_CMDTOUT (1<<10) +#define CSTA_RSPFIN (1<<9) +#define CSTA_CMDON (1<<8) +#define SDI_RSP0 0x14 +#define SDI_RSP1 0x18 +#define SDI_RSP2 0x1c +#define SDI_RSP3 0x20 +#define SDI_DTIMER 0x24 +#define SDI_BSIZE 0x28 +#define SDI_DCON 0x2c +#define DCON_PRDTYPE (1<<21) +#define DCON_TARSP (1<<20) /* Transmit after response */ +#define DCON_RACMD (1<<19) /* Receive after command */ +#define DCON_BACMD (1<<18) /* Busy after command */ +#define DCON_BLKMODE (1<<17) /* Stream/Block mode */ +#define DCON_WIDEBUS (1<<16) /* Standard/Wide bus */ +#define DCON_ENDMA (1<<15) /* DMA Enable */ +/* Determine the direction of the data transfer */ +#define DCON_DATA_READY (0<<12) /* No transfer */ +#define DCON_ONLYBUST (1<<12) /* Check if busy */ +#define DCON_DATA_RECEIVE (2<<12) /* Receive data from SD */ +#define DCON_DATA_TRANSMIT (3<<12) /* Send data to SD */ +#define DCON_BLKNUM_MASK (0x7FF) /* Block number */ +#define SDI_DCNT 0x30 +#define SDI_DSTA 0x34 +#define SDI_FSTA 0x38 + + /* Timer */ #define TIMER_TCFG0 0x00 /* Timer configuration */ #define TIMER_TCFG1 0x04 @@ -333,8 +453,11 @@ /* UART */ /* diffs to s3c2800 */ +/* SSCOM_UMCON */ #define UMCON_AFC (1<<4) /* auto flow control */ +/* SSCOM_UMSTAT */ #define UMSTAT_DCTS (1<<2) /* CTS change */ +/* SSCOM_UMSTAT */ #define ULCON_IR (1<<6) #define ULCON_PARITY_SHIFT 3 @@ -370,6 +493,101 @@ /* IIS */ /* XXX */ #define S3C24X0_IIS_SIZE 0x14 +/* GPIO */ +#define GPIO_PACON 0x00 /* port A configuration */ +#define GPIO_PADAT 0x04 /* port A data */ + +#define GPIO_PBCON 0x10 +/* These are only used on port B-H on 2410 & B-H,J on 2440 */ +#define PCON_INPUT 0 /* Input port */ +#define PCON_OUTPUT 1 /* Output port */ +#define PCON_ALTFUN 2 /* Alternate function */ +#define PCON_ALTFUN2 3 /* Alternate function */ +#define GPIO_PBDAT 0x14 +/* This is different between 2440 and 2442 (pull up vs pull down): */ +#define GPIO_PBUP 0x18 /* 2410 & 2440 */ +#define GPIO_PBDOWN 0x18 /* 2442 */ + +#define GPIO_PCCON 0x20 +#define GPIO_PCDAT 0x24 +#define GPIO_PCUP 0x28 /* 2410 & 2440 */ +#define GPIO_PCDOWN 0x28 /* 2442 */ + +#define GPIO_PDCON 0x30 +#define GPIO_PDDAT 0x34 +#define GPIO_PDUP 0x38 /* 2410 & 2440 */ +#define GPIO_PDDOWN 0x38 /* 2442 */ + +#define GPIO_PECON 0x40 +#define GPIO_PEDAT 0x44 +#define GPIO_PEUP 0x48 /* 2410 & 2440 */ +#define GPIO_PEDOWN 0x48 /* 2442 */ + +#define GPIO_PFCON 0x50 +#define GPIO_PFDAT 0x54 +#define GPIO_PFUP 0x58 /* 2410 & 2440 */ +#define GPIO_PFDOWN 0x58 /* 2442 */ + +#define GPIO_PGCON 0x60 +#define GPIO_PGDAT 0x64 +#define GPIO_PGUP 0x68 /* 2410 & 2440 */ +#define GPIO_PGDOWN 0x68 /* 2442 */ + +#define GPIO_PHCON 0x70 +#define GPIO_PHDAT 0x74 +#define GPIO_PHUP 0x78 /* 2410 & 2440 */ +#define GPIO_PHDOWN 0x78 /* 2442 */ + +#define GPIO_MISCCR 0x80 /* miscellaneous control */ +#define GPIO_DCLKCON 0x84 /* DCLK 0/1 */ +#define GPIO_EXTINT(n) (0x88+4*(n)) /* external int control 0/1/2 */ +#define GPIO_EINTFLT(n) (0x94+4*(n)) /* external int filter control 0..3 */ +#define EXTINTR_LOW 0x00 +#define EXTINTR_HIGH 0x01 +#define EXTINTR_FALLING 0x02 +#define EXTINTR_RISING 0x04 +#define EXTINTR_BOTH 0x06 +#define GPIO_EINTMASK 0xa4 +#define GPIO_EINTPEND 0xa8 +#define GPIO_GSTATUS0 0xac /* external pin status */ +#define GPIO_GSTATUS1 0xb0 /* Chip ID */ +#define GPIO_GSTATUS2 0xb4 /* Reset status */ +#define GPIO_GSTATUS3 0xb8 +#define GPIO_GSTATUS4 0xbc + +#define GPIO_SET_FUNC(v,port,func) \ + (((v) & ~(3<<(2*(port))))|((func)<<(2*(port)))) + +/* ADC */ +#define ADC_ADCCON 0x00 +#define ADCCON_ENABLE_START (1<<0) +#define ADCCON_READ_START (1<<1) +#define ADCCON_STDBM (1<<2) +#define ADCCON_SEL_MUX_SHIFT 3 +#define ADCCON_SEL_MUX_MASK (0x7<<ADCCON_SEL_MUX_SHIFT) +#define ADCCON_PRSCVL_SHIFT 6 +#define ADCCON_PRSCVL_MASK (0xff<<ADCCON_PRSCVL_SHIFT) +#define ADCCON_PRSCEN (1<<14) +#define ADCCON_ECFLG (1<<15) + +#define ADC_ADCTSC 0x04 +#define ADCTSC_XY_PST 0x03 +#define ADCTSC_AUTO_PST (1<<2) +#define ADCTSC_PULL_UP (1<<3) +#define ADCTSC_XP_SEN (1<<4) +#define ADCTSC_XM_SEN (1<<5) +#define ADCTSC_YP_SEN (1<<6) +#define ADCTSC_YM_SEN (1<<7) +#define ADC_ADCDLY 0x08 +#define ADC_ADCDAT0 0x0c +#define ADC_ADCDAT1 0x10 + +#define ADCDAT_DATAMASK 0x3ff + +/* XXX: Move to s3c2440reg.h */ +#define ADCTSC_UD_SEN (1<<8) +#define S3C2440_ADC_SIZE 0x18 + /* RTC */ /* XXX */ /* SPI */
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