From owner-svn-src-head@FreeBSD.ORG Tue Mar 10 10:47:06 2015 Return-Path: Delivered-To: svn-src-head@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:1900:2254:206a::19:1]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by hub.freebsd.org (Postfix) with ESMTPS id 98150A28; Tue, 10 Mar 2015 10:47:06 +0000 (UTC) Received: from zxy.spb.ru (zxy.spb.ru [195.70.199.98]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mx1.freebsd.org (Postfix) with ESMTPS id 5072A668; Tue, 10 Mar 2015 10:47:06 +0000 (UTC) Received: from slw by zxy.spb.ru with local (Exim 4.84 (FreeBSD)) (envelope-from ) id 1YVHgf-0003JI-RS; Tue, 10 Mar 2015 13:46:57 +0300 Date: Tue, 10 Mar 2015 13:46:57 +0300 From: Slawa Olhovchenkov To: Konstantin Belousov Subject: Re: svn commit: r279699 - in head/sys: amd64/amd64 i386/i386 Message-ID: <20150310104657.GA66448@zxy.spb.ru> References: <201503062034.t26KYSP2063973@svn.freebsd.org> <20150309174252.GO2379@kib.kiev.ua> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20150309174252.GO2379@kib.kiev.ua> User-Agent: Mutt/1.5.23 (2014-03-12) X-SA-Exim-Connect-IP: X-SA-Exim-Mail-From: slw@zxy.spb.ru X-SA-Exim-Scanned: No (on zxy.spb.ru); SAEximRunCond expanded to false Cc: svn-src-head@freebsd.org, svn-src-all@freebsd.org, src-committers@freebsd.org, John Baldwin X-BeenThere: svn-src-head@freebsd.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: SVN commit messages for the src tree for head/-current List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 10 Mar 2015 10:47:06 -0000 On Mon, Mar 09, 2015 at 07:42:52PM +0200, Konstantin Belousov wrote: > On Fri, Mar 06, 2015 at 08:34:28PM +0000, John Baldwin wrote: > > Author: jhb > > Date: Fri Mar 6 20:34:28 2015 > > New Revision: 279699 > > URL: https://svnweb.freebsd.org/changeset/base/279699 > > > > Log: > > Only schedule interrupts on a single hyperthread of a modern Intel CPU core > > by default. Previously we used a single hyperthread on Pentium4-era > > cores but used both hyperthreads on more recent CPUs. > > > > MFC after: 2 weeks > > > > Modified: > > head/sys/amd64/amd64/mp_machdep.c > > head/sys/i386/i386/mp_machdep.c > > > > Modified: head/sys/amd64/amd64/mp_machdep.c > > ============================================================================== > > --- head/sys/amd64/amd64/mp_machdep.c Fri Mar 6 16:43:54 2015 (r279698) > > +++ head/sys/amd64/amd64/mp_machdep.c Fri Mar 6 20:34:28 2015 (r279699) > > @@ -828,8 +828,8 @@ set_interrupt_apic_ids(void) > > continue; > > > > /* Don't let hyperthreads service interrupts. */ > > - if (hyperthreading_cpus > 1 && > > - apic_id % hyperthreading_cpus != 0) > > + if (cpu_logical > 1 && > > + apic_id % cpu_logical != 0) > > continue; > > > > intr_add_cpu(i); > > > > Modified: head/sys/i386/i386/mp_machdep.c > > ============================================================================== > > --- head/sys/i386/i386/mp_machdep.c Fri Mar 6 16:43:54 2015 (r279698) > > +++ head/sys/i386/i386/mp_machdep.c Fri Mar 6 20:34:28 2015 (r279699) > > @@ -842,8 +842,8 @@ set_interrupt_apic_ids(void) > > continue; > > > > /* Don't let hyperthreads service interrupts. */ > > - if (hyperthreading_cpus > 1 && > > - apic_id % hyperthreading_cpus != 0) > > + if (cpu_logical > 1 && > > + apic_id % cpu_logical != 0) > > continue; > > > > intr_add_cpu(i); > > BTW, this sounds somewhat backward from the intention of the HTT/SMT. > The feature was aimed to reduce latency of memory or device registers > reads by allowing several contexts to stuck on the cache line fill > or waiting for the device response to read request. > > Since typical interrupt handler just EOIs the source or does nothing at > all to the source, what is the reasoning behind the change ? typical interrupt handler do TCP work?