From owner-p4-projects@FreeBSD.ORG Mon Sep 8 04:53:57 2014 Return-Path: Delivered-To: p4-projects@freebsd.org Received: by hub.freebsd.org (Postfix, from userid 32767) id 92D501D7; Mon, 8 Sep 2014 04:53:57 +0000 (UTC) Delivered-To: perforce@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [8.8.178.115]) (using TLSv1 with cipher ADH-AES256-SHA (256/256 bits)) (No client certificate requested) by hub.freebsd.org (Postfix) with ESMTPS id 8169F53A for ; Mon, 8 Sep 2014 04:52:26 +0000 (UTC) Received: from skunkworks.freebsd.org (skunkworks.freebsd.org [IPv6:2001:1900:2254:2068::682:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mx1.freebsd.org (Postfix) with ESMTPS id 6E8591FF5 for ; Mon, 8 Sep 2014 04:52:26 +0000 (UTC) Received: from skunkworks.freebsd.org ([127.0.1.74]) by skunkworks.freebsd.org (8.14.9/8.14.9) with ESMTP id s884qQ1r029653 for ; Mon, 8 Sep 2014 04:52:26 GMT (envelope-from jhb@freebsd.org) Received: (from perforce@localhost) by skunkworks.freebsd.org (8.14.9/8.14.9/Submit) id s884qQAQ029650 for perforce@freebsd.org; Mon, 8 Sep 2014 04:52:26 GMT (envelope-from jhb@freebsd.org) Date: Mon, 8 Sep 2014 04:52:26 GMT Message-Id: <201409080452.s884qQAQ029650@skunkworks.freebsd.org> X-Authentication-Warning: skunkworks.freebsd.org: perforce set sender to jhb@freebsd.org using -f From: John Baldwin Subject: PERFORCE change 1199791 for review To: Perforce Change Reviews Precedence: bulk X-BeenThere: p4-projects@freebsd.org X-Mailman-Version: 2.1.18-1 List-Id: p4 projects tree changes List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 08 Sep 2014 04:53:57 -0000 http://p4web.freebsd.org/@@1199791?ac=10 Change 1199791 by jhb@jhb_ralph on 2014/09/04 02:02:56 - Collapse init_exthigh() down to match amd64. - Move TSC blacklists into the TSC probe code. Affected files ... .. //depot/projects/smpng/sys/i386/i386/identcpu.c#83 edit .. //depot/projects/smpng/sys/x86/x86/tsc.c#12 edit Differences ... ==== //depot/projects/smpng/sys/i386/i386/identcpu.c#83 (text+ko) ==== @@ -65,7 +65,6 @@ #define IDENTBLUE_CYRIXM2 2 static void identifycyrix(void); -static void init_exthigh(void); static u_int find_cpu_vendor_id(void); static void print_AMD_info(void); static void print_INTEL_info(void); @@ -147,28 +146,6 @@ #endif }; -static void -init_exthigh(void) -{ - static int done = 0; - u_int regs[4]; - - if (done == 0) { - if (cpu_high > 0 && - (cpu_vendor_id == CPU_VENDOR_INTEL || - cpu_vendor_id == CPU_VENDOR_AMD || - cpu_vendor_id == CPU_VENDOR_TRANSMETA || - cpu_vendor_id == CPU_VENDOR_CENTAUR || - cpu_vendor_id == CPU_VENDOR_NSC)) { - do_cpuid(0x80000000, regs); - if (regs[0] >= 0x80000000) - cpu_exthigh = regs[0]; - } - - done = 1; - } -} - void printcpuinfo(void) { @@ -180,7 +157,6 @@ strncpy(cpu_model, i386_cpus[cpu].cpu_name, sizeof (cpu_model)); /* Check for extended CPUID information and a processor name. */ - init_exthigh(); if (cpu_exthigh >= 0x80000004) { brand = cpu_brand; for (i = 0x80000002; i < 0x80000005; i++) { @@ -354,7 +330,6 @@ break; case 0x500: strcat(cpu_model, "K5 model 0"); - tsc_freq = 0; break; case 0x510: strcat(cpu_model, "K5 model 1"); @@ -553,13 +528,6 @@ switch (cpu_id & 0xff0) { case 0x540: strcpy(cpu_model, "IDT WinChip C6"); - /* - * http://www.centtech.com/c6_data_sheet.pdf - * - * I-12 RDTSC may return incoherent values in EDX:EAX - * I-13 RDTSC hangs when certain event counters are used - */ - tsc_freq = 0; break; case 0x580: strcpy(cpu_model, "IDT WinChip 2"); @@ -599,8 +567,6 @@ case 0x540: strcpy(cpu_model, "Geode SC1100"); cpu = CPU_GEODE1100; - if ((cpu_id & CPUID_STEPPING) == 0) - tsc_freq = 0; break; default: strcpy(cpu_model, "Geode/NSC unknown"); @@ -1110,10 +1076,20 @@ cpu_mon_max_size = regs[1] & CPUID5_MON_MAX_SIZE; } + if (cpu_high > 0 && + (cpu_vendor_id == CPU_VENDOR_INTEL || + cpu_vendor_id == CPU_VENDOR_AMD || + cpu_vendor_id == CPU_VENDOR_TRANSMETA || + cpu_vendor_id == CPU_VENDOR_CENTAUR || + cpu_vendor_id == CPU_VENDOR_NSC)) { + do_cpuid(0x80000000, regs); + if (regs[0] >= 0x80000000) + cpu_exthigh = regs[0]; + } + /* Detect AMD features (PTE no-execute bit, 3dnow, 64 bit mode etc) */ if (cpu_vendor_id == CPU_VENDOR_INTEL || cpu_vendor_id == CPU_VENDOR_AMD) { - init_exthigh(); if (cpu_exthigh >= 0x80000001) { do_cpuid(0x80000001, regs); amd_feature = regs[3] & ~(cpu_feature & 0x0183f3ff); @@ -1128,7 +1104,6 @@ cpu_procinfo2 = regs[2]; } } else if (cpu_vendor_id == CPU_VENDOR_CENTAUR) { - init_exthigh(); if (cpu_exthigh >= 0x80000001) { do_cpuid(0x80000001, regs); amd_feature = regs[3] & ~(cpu_feature & 0x0183f3ff); ==== //depot/projects/smpng/sys/x86/x86/tsc.c#12 (text+ko) ==== @@ -324,6 +324,39 @@ if ((cpu_feature & CPUID_TSC) == 0 || tsc_disabled) return; +#ifdef __i386__ + /* The TSC is known to be broken on certain CPUs. */ + switch (cpu_vendor_id) { + case CPU_VENDOR_AMD: + switch (cpu_id & 0xFF0) { + case 0x500: + /* K5 Model 0 */ + return; + } + break; + case CPU_VENDOR_CENTAUR: + switch (cpu_id & 0xff0) { + case 0x540: + /* + * http://www.centtech.com/c6_data_sheet.pdf + * + * I-12 RDTSC may return incoherent values in EDX:EAX + * I-13 RDTSC hangs when certain event counters are used + */ + return; + } + break; + case CPU_VENDOR_NSC: + switch (cpu_id & 0xff0) { + case 0x540: + if ((cpu_id & CPUID_STEPPING) == 0) + return; + break; + } + break; + } +#endif + probe_tsc_freq(); /*