Date: Fri, 15 Jun 2007 23:03:25 +0200 From: John Hay <jhay@meraka.org.za> To: freebsd-arm@freebsd.org Subject: more hints for avila Message-ID: <20070615210325.GA1007@zibbi.meraka.csir.co.za>
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Hi,
This is my latest code to move enough of the ixp425/avila stuff into
hints, so that I can get the Pronghorn metro boards to work just by
changing the hints file.
So what do you guys think?
John
--
John Hay -- John.Hay@meraka.csir.co.za / jhay@FreeBSD.org
Index: conf/AVILA.hints
===================================================================
RCS file: /home/ncvs/src/sys/arm/conf/AVILA.hints,v
retrieving revision 1.2
diff -u -r1.2 AVILA.hints
--- conf/AVILA.hints 29 May 2007 18:10:42 -0000 1.2
+++ conf/AVILA.hints 5 Jun 2007 18:43:53 -0000
@@ -20,12 +20,32 @@
hint.npe.0.at="ixp0"
hint.npe.1.at="ixp0"
+# PCI controller
+#hint.pcib.0.at="ixp0"
+hint.pcib.0.reset=13
+hint.pcib.0.clk=14
+hint.pcib.0.clk66en=-1
+hint.pcib.0.slottop=32
+hint.pcislot.0.irq=28
+hint.pcislot.1.irq=27
+hint.pcislot.2.irq=26
+hint.pcislot.3.irq=25
+
# CF IDE controller
hint.ata_avila.0.at="ixp0"
# LED connected to gpio
hint.led_avila.0.at="ixp0"
+# CLK device
+#hint.ixpclk.0.at="ixp0"
+hint.ixpclk.0.freq=66666600
+
+# IIC controller
+#hint.ixpiic.0.at="ixp0"
+hint.ixpiic.0.scl=6
+hint.ixpiic.0.sda=7
+
# Analog Devices AD7418 temperature sensor
hint.ad7418.0.at="iicbus0"
hint.ad7418.0.addr=0x50
Index: xscale/ixp425/ixdp425_pci.c
===================================================================
RCS file: /home/ncvs/src/sys/arm/xscale/ixp425/ixdp425_pci.c,v
retrieving revision 1.1
diff -u -r1.1 ixdp425_pci.c
--- xscale/ixp425/ixdp425_pci.c 19 Nov 2006 23:55:23 -0000 1.1
+++ xscale/ixp425/ixdp425_pci.c 5 Jun 2007 18:46:52 -0000
@@ -56,59 +56,78 @@
{
struct ixp425_softc *sc = device_get_softc(device_get_parent(dev));
struct ixppcib_softc *pci_sc = device_get_softc(dev);
- uint32_t reg;
+ const char *dname;
+ int dunit;
+ uint32_t inta, intb, intc, intd, reg;
+ uint32_t resetpin, clkpin, clk66pin;
+
+ dname = device_get_name(dev);
+ dunit = device_get_unit(dev);
+ resource_int_value(dname , dunit, "reset", &resetpin);
+ resource_int_value(dname , dunit, "clk", &clkpin);
+ resource_int_value(dname , dunit, "clk66en", &clk66pin);
+ resource_int_value("pcislot", 0, "irq", &inta);
+ resource_int_value("pcislot", 1, "irq", &intb);
+ resource_int_value("pcislot", 2, "irq", &intc);
+ resource_int_value("pcislot", 3, "irq", &intd);
-
/* PCI Reset Assert */
reg = GPIO_CONF_READ_4(sc, IXP425_GPIO_GPOUTR);
- reg &= ~(1U << GPIO_PCI_RESET);
- GPIO_CONF_WRITE_4(sc, IXP425_GPIO_GPOUTR, reg & ~(1U << GPIO_PCI_RESET));
+ reg &= ~(1U << resetpin);
+ GPIO_CONF_WRITE_4(sc, IXP425_GPIO_GPOUTR, reg);
/* PCI Clock Disable */
reg = GPIO_CONF_READ_4(sc, IXP425_GPIO_GPCLKR);
reg &= ~GPCLKR_MUX14;
GPIO_CONF_WRITE_4(sc, IXP425_GPIO_GPCLKR, reg & ~GPCLKR_MUX14);
+ /* Not all support 66MHz pci clock. */
+ if (clk66pin != -1) {
+ reg = GPIO_CONF_READ_4(sc, IXP425_GPIO_GPOUTR);
+ reg &= ~(1U << clk66pin);
+ GPIO_CONF_WRITE_4(sc, IXP425_GPIO_GPOUTR, reg);
+ }
+
/*
* set GPIO Direction
- * Output: PCI_CLK, PCI_RESET
+ * Output: (PCI_CLK66_EN), PCI_CLK, PCI_RESET
* Input: PCI_INTA, PCI_INTB, PCI_INTC, PCI_INTD
*/
reg = GPIO_CONF_READ_4(sc, IXP425_GPIO_GPOER);
- reg &= ~(1U << GPIO_PCI_CLK);
- reg &= ~(1U << GPIO_PCI_RESET);
- reg |= ((1U << GPIO_PCI_INTA) | (1U << GPIO_PCI_INTB) |
- (1U << GPIO_PCI_INTC) | (1U << GPIO_PCI_INTD));
+ if (clk66pin != -1)
+ reg &= ~(1U << clk66pin);
+ reg &= ~(1U << clkpin);
+ reg &= ~(1U << resetpin);
+ reg |= ((1U << inta) | (1U << intb) | (1U << intc) | (1U << intd));
GPIO_CONF_WRITE_4(sc, IXP425_GPIO_GPOER, reg);
/*
* Set GPIO interrupt type
* PCI_INT_A, PCI_INTB, PCI_INT_C, PCI_INT_D: Active Low
*/
- reg = GPIO_CONF_READ_4(sc, GPIO_TYPE_REG(GPIO_PCI_INTA));
- reg &= ~GPIO_TYPE(GPIO_PCI_INTA, GPIO_TYPE_MASK);
- reg |= GPIO_TYPE(GPIO_PCI_INTA, GPIO_TYPE_ACT_LOW);
- GPIO_CONF_WRITE_4(sc, GPIO_TYPE_REG(GPIO_PCI_INTA), reg);
-
- reg = GPIO_CONF_READ_4(sc, GPIO_TYPE_REG(GPIO_PCI_INTB));
- reg &= ~GPIO_TYPE(GPIO_PCI_INTB, GPIO_TYPE_MASK);
- reg |= GPIO_TYPE(GPIO_PCI_INTB, GPIO_TYPE_ACT_LOW);
- GPIO_CONF_WRITE_4(sc, GPIO_TYPE_REG(GPIO_PCI_INTB), reg);
-
- reg = GPIO_CONF_READ_4(sc, GPIO_TYPE_REG(GPIO_PCI_INTC));
- reg &= ~GPIO_TYPE(GPIO_PCI_INTC, GPIO_TYPE_MASK);
- reg |= GPIO_TYPE(GPIO_PCI_INTC, GPIO_TYPE_ACT_LOW);
- GPIO_CONF_WRITE_4(sc, GPIO_TYPE_REG(GPIO_PCI_INTC), reg);
-
- reg = GPIO_CONF_READ_4(sc, GPIO_TYPE_REG(GPIO_PCI_INTD));
- reg &= ~GPIO_TYPE(GPIO_PCI_INTD, GPIO_TYPE_MASK);
- reg |= GPIO_TYPE(GPIO_PCI_INTD, GPIO_TYPE_ACT_LOW);
- GPIO_CONF_WRITE_4(sc, GPIO_TYPE_REG(GPIO_PCI_INTD), reg);
+ reg = GPIO_CONF_READ_4(sc, GPIO_TYPE_REG(inta));
+ reg &= ~GPIO_TYPE(inta, GPIO_TYPE_MASK);
+ reg |= GPIO_TYPE(inta, GPIO_TYPE_ACT_LOW);
+ GPIO_CONF_WRITE_4(sc, GPIO_TYPE_REG(inta), reg);
+
+ reg = GPIO_CONF_READ_4(sc, GPIO_TYPE_REG(intb));
+ reg &= ~GPIO_TYPE(intb, GPIO_TYPE_MASK);
+ reg |= GPIO_TYPE(intb, GPIO_TYPE_ACT_LOW);
+ GPIO_CONF_WRITE_4(sc, GPIO_TYPE_REG(intb), reg);
+
+ reg = GPIO_CONF_READ_4(sc, GPIO_TYPE_REG(intc));
+ reg &= ~GPIO_TYPE(intc, GPIO_TYPE_MASK);
+ reg |= GPIO_TYPE(intc, GPIO_TYPE_ACT_LOW);
+ GPIO_CONF_WRITE_4(sc, GPIO_TYPE_REG(intc), reg);
+
+ reg = GPIO_CONF_READ_4(sc, GPIO_TYPE_REG(intd));
+ reg &= ~GPIO_TYPE(intd, GPIO_TYPE_MASK);
+ reg |= GPIO_TYPE(intd, GPIO_TYPE_ACT_LOW);
+ GPIO_CONF_WRITE_4(sc, GPIO_TYPE_REG(intd), reg);
/* clear ISR */
GPIO_CONF_WRITE_4(sc, IXP425_GPIO_GPISR,
- (1U << GPIO_PCI_INTA) | (1U << GPIO_PCI_INTB) |
- (1U << GPIO_PCI_INTC) | (1U << GPIO_PCI_INTD));
+ (1U << inta) | (1U << intb) | (1U << intc) | (1U << intd));
/* wait 1ms to satisfy "minimum reset assertion time" of the PCI spec */
DELAY(1000);
@@ -119,7 +138,7 @@
/* PCI Clock Enable */
reg = GPIO_CONF_READ_4(sc, IXP425_GPIO_GPCLKR);
reg |= GPCLKR_MUX14;
- GPIO_CONF_WRITE_4(sc, IXP425_GPIO_GPCLKR, reg | GPCLKR_MUX14);
+ GPIO_CONF_WRITE_4(sc, IXP425_GPIO_GPCLKR, reg);
/*
* wait 100us to satisfy "minimum reset assertion time from clock stable
@@ -128,14 +147,21 @@
DELAY(100);
/* PCI Reset deassert */
reg = GPIO_CONF_READ_4(sc, IXP425_GPIO_GPOUTR);
- reg |= 1U << GPIO_PCI_RESET;
- GPIO_CONF_WRITE_4(sc, IXP425_GPIO_GPOUTR, reg | (1U << GPIO_PCI_RESET));
+ reg |= 1U << resetpin;
+ GPIO_CONF_WRITE_4(sc, IXP425_GPIO_GPOUTR, reg);
pci_sc->sc_irq_rman.rm_type = RMAN_ARRAY;
pci_sc->sc_irq_rman.rm_descr = "IXP425 PCI IRQs";
- CTASSERT(PCI_INT_D < PCI_INT_A);
- /* XXX this overlaps the irq's setup in ixp425_attach */
+ /*
+ * XXX this overlaps the irq's setup in ixp425_attach
+ *
+ * PCI irq's on the Pronghorn are not consecutive, so do
+ * them one at a time.
+ */
if (rman_init(&pci_sc->sc_irq_rman) != 0 ||
- rman_manage_region(&pci_sc->sc_irq_rman, PCI_INT_D, PCI_INT_A) != 0)
+ rman_manage_region(&pci_sc->sc_irq_rman, inta, inta) != 0 ||
+ rman_manage_region(&pci_sc->sc_irq_rman, intb, intb) != 0 ||
+ rman_manage_region(&pci_sc->sc_irq_rman, intc, intc) != 0 ||
+ rman_manage_region(&pci_sc->sc_irq_rman, intd, intd) != 0)
panic("ixp425_md_attach: failed to set up IRQ rman");
}
@@ -145,23 +171,38 @@
int
ixp425_md_route_interrupt(device_t bridge, device_t device, int pin)
{
- static int ixp425_pci_table[IXP425_MAX_DEV][IXP425_MAX_LINE] =
- {
- {PCI_INT_A, PCI_INT_B, PCI_INT_C, PCI_INT_D},
- {PCI_INT_B, PCI_INT_C, PCI_INT_D, PCI_INT_A},
- {PCI_INT_C, PCI_INT_D, PCI_INT_A, PCI_INT_B},
- {PCI_INT_D, PCI_INT_A, PCI_INT_B, PCI_INT_C},
- };
- int dev;
-
+ static int ixp425_pci_table[IXP425_MAX_DEV][IXP425_MAX_LINE];
+ static int table_filled = 0;
+ int di, dev, li;
+
+ if (table_filled == 0) {
+ resource_int_value("pcislot", 0, "irq", &di);
+ ixp425_pci_table[0][0] = di;
+ resource_int_value("pcislot", 1, "irq", &di);
+ ixp425_pci_table[0][1] = di;
+ resource_int_value("pcislot", 2, "irq", &di);
+ ixp425_pci_table[0][2] = di;
+ resource_int_value("pcislot", 3, "irq", &di);
+ ixp425_pci_table[0][3] = di;
+ if (bootverbose)
+ device_printf(bridge, "irq list a %d, b %d, c %d, d %d\n",
+ ixp425_pci_table[0][0], ixp425_pci_table[0][1],
+ ixp425_pci_table[0][2], ixp425_pci_table[0][3]);
+ for (di = 1; di < IXP425_MAX_DEV; di++)
+ for (li = 0; li < IXP425_MAX_LINE; li++)
+ ixp425_pci_table[di][li] =
+ ixp425_pci_table[0][(di + li) %
+ IXP425_MAX_LINE];
+ table_filled = 1;
+ }
dev = pci_get_slot(device);
if (bootverbose)
device_printf(bridge, "routing pin %d for %s\n", pin,
device_get_nameunit(device));
if (pin >= 1 && pin <= IXP425_MAX_LINE &&
- dev >= 1 && dev <= IXP425_MAX_DEV) {
+ dev >= 1 && dev <= IXP425_MAX_DEV)
return (ixp425_pci_table[dev - 1][pin - 1]);
- } else
+ else
printf("ixppcib: no mapping for %d/%d/%d\n",
pci_get_bus(device), dev, pci_get_function(device));
Index: xscale/ixp425/ixp425_iic.c
===================================================================
RCS file: /home/ncvs/src/sys/arm/xscale/ixp425/ixp425_iic.c,v
retrieving revision 1.1
diff -u -r1.1 ixp425_iic.c
--- xscale/ixp425/ixp425_iic.c 19 Nov 2006 23:55:23 -0000 1.1
+++ xscale/ixp425/ixp425_iic.c 28 May 2007 19:36:47 -0000
@@ -61,6 +61,8 @@
device_t sc_dev;
bus_space_tag_t sc_iot;
bus_space_handle_t sc_gpio_ioh;
+ uint32_t sc_scl_bit;
+ uint32_t sc_sda_bit;
device_t iicbb;
};
@@ -79,17 +81,25 @@
{
struct ixpiic_softc *sc = device_get_softc(dev);
struct ixp425_softc *sa = device_get_softc(device_get_parent(dev));
+ const char *dname;
+ int dunit;
ixpiic_sc = sc;
sc->sc_dev = dev;
sc->sc_iot = sa->sc_iot;
sc->sc_gpio_ioh = sa->sc_gpio_ioh;
+ dname = device_get_name(dev);
+ dunit = device_get_unit(dev);
+ resource_int_value(dname, dunit, "scl", &sc->sc_scl_bit);
+ sc->sc_scl_bit = 1U << sc->sc_scl_bit;
+ resource_int_value(dname, dunit, "sda", &sc->sc_sda_bit);
+ sc->sc_sda_bit = 1U << sc->sc_sda_bit;
GPIO_CONF_SET(sc, IXP425_GPIO_GPOER,
- GPIO_I2C_SCL_BIT | GPIO_I2C_SDA_BIT);
+ sc->sc_scl_bit | sc->sc_sda_bit);
GPIO_CONF_CLR(sc, IXP425_GPIO_GPOUTR,
- GPIO_I2C_SCL_BIT | GPIO_I2C_SDA_BIT);
+ sc->sc_scl_bit | sc->sc_sda_bit);
/* add generic bit-banging code */
if ((sc->iicbb = device_add_child(dev, "iicbb", -1)) == NULL)
@@ -113,10 +123,10 @@
struct ixpiic_softc *sc = ixpiic_sc;
uint32_t reg;
- GPIO_CONF_SET(sc, IXP425_GPIO_GPOER, GPIO_I2C_SCL_BIT);
+ GPIO_CONF_SET(sc, IXP425_GPIO_GPOER, sc->sc_scl_bit);
reg = GPIO_CONF_READ_4(sc, IXP425_GPIO_GPINR);
- return (reg & GPIO_I2C_SCL_BIT);
+ return (reg & sc->sc_scl_bit);
}
static int
@@ -125,10 +135,10 @@
struct ixpiic_softc *sc = ixpiic_sc;
uint32_t reg;
- GPIO_CONF_SET(sc, IXP425_GPIO_GPOER, GPIO_I2C_SDA_BIT);
+ GPIO_CONF_SET(sc, IXP425_GPIO_GPOER, sc->sc_sda_bit);
reg = GPIO_CONF_READ_4(sc, IXP425_GPIO_GPINR);
- return (reg & GPIO_I2C_SDA_BIT);
+ return (reg & sc->sc_sda_bit);
}
static void
@@ -136,11 +146,11 @@
{
struct ixpiic_softc *sc = ixpiic_sc;
- GPIO_CONF_CLR(sc, IXP425_GPIO_GPOUTR, GPIO_I2C_SDA_BIT);
+ GPIO_CONF_CLR(sc, IXP425_GPIO_GPOUTR, sc->sc_sda_bit);
if (val)
- GPIO_CONF_SET(sc, IXP425_GPIO_GPOER, GPIO_I2C_SDA_BIT);
+ GPIO_CONF_SET(sc, IXP425_GPIO_GPOER, sc->sc_sda_bit);
else
- GPIO_CONF_CLR(sc, IXP425_GPIO_GPOER, GPIO_I2C_SDA_BIT);
+ GPIO_CONF_CLR(sc, IXP425_GPIO_GPOER, sc->sc_sda_bit);
DELAY(I2C_DELAY);
}
@@ -149,11 +159,11 @@
{
struct ixpiic_softc *sc = ixpiic_sc;
- GPIO_CONF_CLR(sc, IXP425_GPIO_GPOUTR, GPIO_I2C_SCL_BIT);
+ GPIO_CONF_CLR(sc, IXP425_GPIO_GPOUTR, sc->sc_scl_bit);
if (val)
- GPIO_CONF_SET(sc, IXP425_GPIO_GPOER, GPIO_I2C_SCL_BIT);
+ GPIO_CONF_SET(sc, IXP425_GPIO_GPOER, sc->sc_scl_bit);
else
- GPIO_CONF_CLR(sc, IXP425_GPIO_GPOER, GPIO_I2C_SCL_BIT);
+ GPIO_CONF_CLR(sc, IXP425_GPIO_GPOER, sc->sc_scl_bit);
DELAY(I2C_DELAY);
}
Index: xscale/ixp425/ixp425_pci.c
===================================================================
RCS file: /home/ncvs/src/sys/arm/xscale/ixp425/ixp425_pci.c,v
retrieving revision 1.4
diff -u -r1.4 ixp425_pci.c
--- xscale/ixp425/ixp425_pci.c 6 Mar 2007 10:58:22 -0000 1.4
+++ xscale/ixp425/ixp425_pci.c 28 May 2007 19:43:51 -0000
@@ -109,6 +109,8 @@
{
int rid;
struct ixppcib_softc *sc;
+ const char *dname;
+ int dunit;
sc = device_get_softc(dev);
@@ -213,6 +215,10 @@
IXPPCIB_WRITE_CONF(sc, PCIR_COMMAND,
PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN);
+ dname = device_get_name(dev);
+ dunit = device_get_unit(dev);
+ resource_int_value(dname, dunit, "slottop", &sc->sc_slot_top);
+
/*
* Wait some more to ensure PCI devices have stabilised.
*/
@@ -355,8 +361,9 @@
slot &= 0x1f;
func &= 0x07;
/* configuration type 0 */
- PCI_CSR_WRITE_4(sc, PCI_NP_AD, (1U << (32 - slot)) |
- (func << 8) | (reg & ~3));
+ PCI_CSR_WRITE_4(sc, PCI_NP_AD,
+ (1U << (sc->sc_slot_top - slot)) |
+ (func << 8) | (reg & ~3));
}
} else {
/* configuration type 1 */
Index: xscale/ixp425/ixp425_timer.c
===================================================================
RCS file: /home/ncvs/src/sys/arm/xscale/ixp425/ixp425_timer.c,v
retrieving revision 1.2
diff -u -r1.2 ixp425_timer.c
--- xscale/ixp425/ixp425_timer.c 23 Feb 2007 12:18:28 -0000 1.2
+++ xscale/ixp425/ixp425_timer.c 5 Jun 2007 20:07:09 -0000
@@ -44,6 +44,7 @@
#include <sys/bus.h>
#include <sys/resource.h>
#include <sys/rman.h>
+#include <sys/sysctl.h>
#include <sys/timetc.h>
#include <machine/bus.h>
@@ -55,7 +56,9 @@
#include <arm/xscale/ixp425/ixp425reg.h>
#include <arm/xscale/ixp425/ixp425var.h>
+static uint32_t ixp425_freq;
static uint32_t counts_per_hz;
+static uint32_t counts_per_usec = 66;
/* callback functions for intr_functions */
int ixpclk_intr(void *);
@@ -68,13 +71,7 @@
};
static unsigned ixp425_timer_get_timecount(struct timecounter *tc);
-
-#ifndef IXP425_CLOCK_FREQ
-#define COUNTS_PER_SEC 66666600 /* 66MHz */
-#else
-#define COUNTS_PER_SEC IXP425_CLOCK_FREQ
-#endif
-#define COUNTS_PER_USEC ((COUNTS_PER_SEC / 1000000) + 1)
+static int sysctl_machdep_ixp425_freq(SYSCTL_HANDLER_ARGS);
static struct ixpclk_softc *ixpclk_sc = NULL;
@@ -85,7 +82,7 @@
ixp425_timer_get_timecount, /* get_timecount */
NULL, /* no poll_pps */
~0u, /* counter_mask */
- COUNTS_PER_SEC, /* frequency */
+ 0, /* frequency */
"IXP425 Timer", /* name */
1000, /* quality */
};
@@ -150,11 +147,18 @@
struct ixpclk_softc* sc = ixpclk_sc;
struct resource *irq;
device_t dev = sc->sc_dev;
+ const char *dname;
u_int oldirqstate;
- int rid = 0;
+ int dunit, rid = 0;
void *ihl;
- if (hz < 50 || COUNTS_PER_SEC % hz) {
+ dname = device_get_name(dev);
+ dunit = device_get_unit(dev);
+ resource_int_value(dname, dunit, "freq", &ixp425_freq);
+ ixp425_timer_timecounter.tc_frequency = ixp425_freq;
+ counts_per_usec = ((ixp425_freq / 1000000) + 1);
+
+ if (hz < 50 || ixp425_freq % hz) {
printf("Cannot get %d Hz clock; using 100 Hz\n", hz);
hz = 100;
}
@@ -192,7 +196,7 @@
OST_WARM_RESET | OST_WDOG_INT | OST_TS_INT |
OST_TIM1_INT | OST_TIM0_INT);
- counts_per_hz = COUNTS_PER_SEC / hz;
+ counts_per_hz = ixp425_freq / hz;
/* reload value & Timer enable */
bus_space_write_4(sc->sc_iot, sc->sc_ioh, IXP425_OST_TIM0_RELOAD,
@@ -224,10 +228,10 @@
* near that length of time and if they are, they should be hung
* out to dry.
*/
- if (n >= (0x80000000U / COUNTS_PER_USEC))
- usecs = (0x80000000U / COUNTS_PER_USEC) - 1;
+ if (n >= (0x80000000U / counts_per_usec))
+ usecs = (0x80000000U / counts_per_usec) - 1;
else
- usecs = n * COUNTS_PER_USEC;
+ usecs = n * counts_per_usec;
/* Note: Timestamp timer counts *up*, unlike the other timers */
first = GET_TS_VALUE();
@@ -266,3 +270,33 @@
cpu_stopprofclock(void)
{
}
+
+static int
+sysctl_machdep_ixp425_freq(SYSCTL_HANDLER_ARGS)
+{
+ struct ixpclk_softc* sc = ixpclk_sc;
+ int error;
+ uint32_t freq;
+
+ if (ixp425_timer_timecounter.tc_frequency == 0)
+ return (EOPNOTSUPP);
+ freq = ixp425_freq;
+ error = sysctl_handle_int(oidp, &freq, 0, req);
+ if (error == 0 && req->newptr != NULL) {
+ ixp425_freq = freq;
+ ixp425_timer_timecounter.tc_frequency = ixp425_freq;
+
+ counts_per_hz = ixp425_freq / hz;
+ counts_per_usec = ((ixp425_freq / 1000000) + 1);
+
+ /* reload value & Timer enable */
+ bus_space_write_4(sc->sc_iot, sc->sc_ioh,
+ IXP425_OST_TIM0_RELOAD,
+ (counts_per_hz & TIMERRELOAD_MASK) | OST_TIMER_EN);
+
+ }
+ return (error);
+}
+
+SYSCTL_PROC(_machdep, OID_AUTO, ixp425_freq, CTLTYPE_INT | CTLFLAG_RW,
+ 0, sizeof(u_int), sysctl_machdep_ixp425_freq, "IU", "");
Index: xscale/ixp425/ixp425var.h
===================================================================
RCS file: /home/ncvs/src/sys/arm/xscale/ixp425/ixp425var.h,v
retrieving revision 1.4
diff -u -r1.4 ixp425var.h
--- xscale/ixp425/ixp425var.h 29 May 2007 18:10:42 -0000 1.4
+++ xscale/ixp425/ixp425var.h 29 May 2007 19:37:42 -0000
@@ -75,6 +75,8 @@
struct bus_space sc_pci_memt;
struct bus_space sc_pci_iot;
bus_dma_tag_t sc_dmat;
+
+ u_int sc_slot_top; /* Where to start the search */
};
#define EXP_BUS_WRITE_4(sc, reg, data) \
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