From owner-freebsd-arm@FreeBSD.ORG Mon May 25 00:35:33 2015 Return-Path: Delivered-To: freebsd-arm@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:1900:2254:206a::19:1]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by hub.freebsd.org (Postfix) with ESMTPS id 5FF68E19; Mon, 25 May 2015 00:35:33 +0000 (UTC) (envelope-from gonzo@id.bluezbox.com) Received: from id.bluezbox.com (id.bluezbox.com [88.198.91.248]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by mx1.freebsd.org (Postfix) with ESMTPS id C6A4FF17; Mon, 25 May 2015 00:35:32 +0000 (UTC) (envelope-from gonzo@id.bluezbox.com) Received: from [208.184.220.60] (helo=macbook-air-2.dolby.net) by id.bluezbox.com with esmtpsa (TLSv1:AES256-SHA:256) (Exim 4.77 (FreeBSD)) (envelope-from ) id 1YwgMa-000DpD-5C; Sun, 24 May 2015 17:35:30 -0700 Content-Type: text/plain; charset=utf-8 Mime-Version: 1.0 (Mac OS X Mail 8.2 \(2098\)) Subject: Re: panic: arm_unmask_irq [was: Re: TI platforms code update: switching to vendor FDT data] From: Oleksandr Tymoshenko In-Reply-To: <1432512966.1200.15.camel@freebsd.org> Date: Sun, 24 May 2015 17:34:55 -0700 Cc: "freebsd-arm@freebsd.org List" Content-Transfer-Encoding: quoted-printable Message-Id: References: <72E1D87A-1CEF-4719-907E-CF8E9D720FD1@xcllnt.net> <3741A6A7-1185-4E5A-9E98-22F5A6C730DC@freebsd.org> <1432512966.1200.15.camel@freebsd.org> To: Ian Lepore X-Mailer: Apple Mail (2.2098) Sender: gonzo@id.bluezbox.com X-Spam-Level: -- X-Spam-Report: Spam detection software, running on the system "id.bluezbox.com", has identified this incoming email as possible spam. The original message has been attached to this so you can view it (if it isn't spam) or label similar future email. If you have any questions, see The administrator of that system for details. Content preview: > On May 24, 2015, at 5:16 PM, Ian Lepore wrote: > > On Sun, 2015-05-24 at 17:12 -0700, Oleksandr Tymoshenko wrote: >>> On May 24, 2015, at 5:05 PM, Marcel Moolenaar wrote: >>> >>> >>>> On May 21, 2015, at 8:37 PM, Oleksandr Tymoshenko wrote: >>>> >>>> Hello, >>>> >>>> I've just committed (r283276) major code update for TI platforms >>>> support. It gets rid of custom-baked .dts files for >>>> Beaglebone/Pandaboard and switches to using FDT data provided by >>>> TI and/or boards/capes manufacturers. >>> >>> *snip* >>> >>> It seems the interrupt controller isn’t been probed and attached >>> in time on my BBB: >>> >>> Booting [/boot/kernel/kernel]... >>> Using DTB provided by U-Boot at address 0x80000100. >>> Kernel entry at 0x80200100... >>> Kernel args: (null) >>> KDB: debugger backends: ddb >>> KDB: current backend: ddb >>> Copyright (c) 1992-2015 The FreeBSD Project. >>> Copyright (c) 1979, 1980, 1983, 1986, 1988, 1989, 1991, 1992, 1993, 1994 >>> The Regents of the University of California. All rights reserved. >>> FreeBSD is a registered trademark of The FreeBSD Foundation. >>> FreeBSD 11.0-CURRENT #1 r283321M: Sun May 24 16:58:54 PDT 2015 >>> marcel@fbsdvm64:/usr/obj/arm.armv6/host/head/sys/BEAGLEBONE arm >>> FreeBSD clang version 3.6.0 (tags/RELEASE_360/final 230434) 20150225 >>> WARNING: WITNESS option enabled, expect reduced performance. >>> can't re-use a leaf (geom_label)! >>> module_register: module g_label already exists! >>> Module g_label failed to register: 17 >>> CPU: Cortex A8-r3 rev 2 (Cortex-A core) >>> Supported features: ARM_ISA THUMB2 JAZELLE THUMBEE ARMv4 Security_Ext >>> WB disabled EABT branch prediction enabled >>> LoUU:2 LoC:3 LoUIS:1 >>> Cache level 1: >>> 32KB/64B 4-way data cache WT WB Read-Alloc >>> 32KB/64B 4-way instruction cache Read-Alloc >>> Cache level 2: >>> 256KB/64B 8-way unified cache WT WB Read-Alloc Write-Alloc >>> real memory = 536870912 (512 MB) >>> avail memory = 513081344 (489 MB) >>> Texas Instruments AM335x [...] Content analysis details: (-2.9 points, 5.0 required) pts rule name description ---- ---------------------- -------------------------------------------------- -1.0 ALL_TRUSTED Passed through trusted hosts only via SMTP 0.0 URIBL_BLOCKED ADMINISTRATOR NOTICE: The query to URIBL was blocked. See http://wiki.apache.org/spamassassin/DnsBlocklists#dnsbl-block for more information. [URIs: xcllnt.net] -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] X-BeenThere: freebsd-arm@freebsd.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: "Porting FreeBSD to ARM processors." List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 25 May 2015 00:35:33 -0000 > On May 24, 2015, at 5:16 PM, Ian Lepore wrote: >=20 > On Sun, 2015-05-24 at 17:12 -0700, Oleksandr Tymoshenko wrote: >>> On May 24, 2015, at 5:05 PM, Marcel Moolenaar = wrote: >>>=20 >>>=20 >>>> On May 21, 2015, at 8:37 PM, Oleksandr Tymoshenko = wrote: >>>>=20 >>>> Hello, >>>>=20 >>>> I've just committed (r283276) major code update for TI platforms >>>> support. It gets rid of custom-baked .dts files for >>>> Beaglebone/Pandaboard and switches to using FDT data provided by >>>> TI and/or boards/capes manufacturers. >>>=20 >>> *snip* >>>=20 >>> It seems the interrupt controller isn=E2=80=99t been probed and = attached >>> in time on my BBB: >>>=20 >>> Booting [/boot/kernel/kernel]... >>> Using DTB provided by U-Boot at address 0x80000100. >>> Kernel entry at 0x80200100... >>> Kernel args: (null) >>> KDB: debugger backends: ddb >>> KDB: current backend: ddb >>> Copyright (c) 1992-2015 The FreeBSD Project. >>> Copyright (c) 1979, 1980, 1983, 1986, 1988, 1989, 1991, 1992, 1993, = 1994 >>> The Regents of the University of California. All rights = reserved. >>> FreeBSD is a registered trademark of The FreeBSD Foundation. >>> FreeBSD 11.0-CURRENT #1 r283321M: Sun May 24 16:58:54 PDT 2015 >>> marcel@fbsdvm64:/usr/obj/arm.armv6/host/head/sys/BEAGLEBONE arm >>> FreeBSD clang version 3.6.0 (tags/RELEASE_360/final 230434) 20150225 >>> WARNING: WITNESS option enabled, expect reduced performance. >>> can't re-use a leaf (geom_label)! >>> module_register: module g_label already exists! >>> Module g_label failed to register: 17 >>> CPU: Cortex A8-r3 rev 2 (Cortex-A core) >>> Supported features: ARM_ISA THUMB2 JAZELLE THUMBEE ARMv4 = Security_Ext >>> WB disabled EABT branch prediction enabled >>> LoUU:2 LoC:3 LoUIS:1 >>> Cache level 1: >>> 32KB/64B 4-way data cache WT WB Read-Alloc >>> 32KB/64B 4-way instruction cache Read-Alloc >>> Cache level 2: >>> 256KB/64B 8-way unified cache WT WB Read-Alloc Write-Alloc >>> real memory =3D 536870912 (512 MB) >>> avail memory =3D 513081344 (489 MB) >>> Texas Instruments AM335x Processor, Revision ES1.2 >>> random: entropy device infrastructure driver >>> random: selecting highest priority adaptor >>> random: SOFT: yarrow init() >>> random: selecting highest priority adaptor >>> ofwbus0: >>> simplebus0: on ofwbus0 >>> am335x_rtc0: mem = 0x44e3e000-0x44e3efff irq 75,76 on simplebus0 >>> am335x_rtc0: AM335X RTC v1.0.6 >>> ti_wdt0: mem 0x44e35000-0x44e35fff irq 91 on = simplebus0 >>> Fatal kernel mode data abort: 'Translation Fault (L1)' on read >>> trapframe: 0xc090ac68 >>> FSR=3D00000005, FAR=3D00000010, spsr=3Da0000193 >>> r0 =3D0000001b, r1 =3D00000001, r2 =3Dc2952e48, r3 =3D08000000 >>> r4 =3D00000040, r5 =3D00000000, r6 =3D0000005b, r7 =3D00000310 >>> r8 =3Dc2ae11c0, r9 =3Dc0605974, r10=3D00000000, r11=3Dc090ad00 >>> r12=3Dc0788b34, ssp=3Dc090acf8, slr=3Dc05f72a8, pc =3Dc05f72b8 >>>=20 >>> [ thread pid 0 tid 100000 ] >>> Stopped at arm_unmask_irq+0x30: ldr r0, [r5, #0x010] >>> db> >>>=20 >>>=20 >>> I=E2=80=99ll poke at it some more, so for now it=E2=80=99s an FYI. >>=20 >> ti_scm and ti_pinmux should be detected right after simplebus. >> Could you make sure if dtb loaded by u-boot is not >> from previous builds? You can decompile it using dtc: >> dtc -I dtb -O dts beaglebone-black.dtb >=20 > Shouldn't the driver attach order be controlled with BUS_PASS numbers > now? That's been required with other socs that moved to the standard > dts data where we don't control the order of the nodes in the file. I believe they should (and most likely they do, can't check right now). My point was - order of devices in dmesg is deterministic, so lack of ti_scm and ti_pinmux most likely indicates that dtb file is not the same as my BBB uses (beaglebone-black.dtb compile from FreeBSD tree). So I wanted to know the content of that file before digging = further.=20=