Date: Fri, 09 Jan 98 09:32:01 -0500 From: "Richard Seaman, Jr." <lists@tar.com> To: "Greg Lehey" <grog@lemis.com>, "Mike Smith" <mike@smith.net.au> Cc: "hardware@FreeBSD.ORG" <hardware@FreeBSD.ORG> Subject: Re: LS-120, Riva 128, ASUS motherboard Message-ID: <199801091532.JAA17368@ns.tar.com>
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On Fri, 9 Jan 1998 19:40:06 +1030, Greg Lehey wrote: >Ahh. http://www.intel.com/design/pcisets/datashts/290559.htm. >Extract: > > The Intel 430TX PCIset (430TX) consists of the 82439TX System > Controller (MTXC) and the 82371AB PCI ISA IDE Xcelerator > (PIIX4). [...] The MTXC integrates the cache and main memory DRAM > control functions and provides bus control to transfers between the > CPU, cache, main memory, and the PCI Bus. The second level (L2) > cache controller supports a writeback cache policy for cache sizes > of 256 Kbytes and 512 Kbytes. > >I'm downloading the document, and will print it out, but this >certainly doesn't sound like Tom's Hardware Guide. >From http://www.intel.com/design/pcisets/datashts/29055901.pdf, page 46: Cacheability of the entire memory space in first level cache is supported, while only the lower 64 MB of main memory is cacheable in the second level cache.
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