Date: Sun, 30 Dec 2018 20:16:26 -0700 From: Ian Lepore <ian@freebsd.org> To: SAITOU Toshihide <toshi@ruby.ocn.ne.jp>, freebsd-arm@freebsd.org Subject: Re: SPI start bit (9 bit) for BBB Message-ID: <1546226186.78877.97.camel@freebsd.org> In-Reply-To: <20181231.003356.1147810385398844555.toshi@ruby.ocn.ne.jp> References: <20181231.003356.1147810385398844555.toshi@ruby.ocn.ne.jp>
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On Mon, 2018-12-31 at 00:33 +0900, SAITOU Toshihide wrote:
> In 3-line serial protcol, there is a type using additional 1-bit to
> specify command or data. The BBB can handle this, so I can use with
> the following patch (unskillful and maybe side effects exist). I
> hope this will attract someones interest to implement this and also
> SPI frequency and mode.
>
Since you are already set up for testing spi on BBB, could you please
try the attached patch for handling bus speed and mode? If it works
I'll get it committed.
-- Ian
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Index: sys/arm/ti/ti_spi.c
===================================================================
--- sys/arm/ti/ti_spi.c (revision 341650)
+++ sys/arm/ti/ti_spi.c (working copy)
@@ -446,7 +446,7 @@ ti_spi_transfer(device_t dev, device_t child, stru
{
int err;
struct ti_spi_softc *sc;
- uint32_t reg, cs;
+ uint32_t clockhz, cs, mode, reg;
sc = device_get_softc(dev);
@@ -457,6 +457,8 @@ ti_spi_transfer(device_t dev, device_t child, stru
/* Get the proper chip select for this child. */
spibus_get_cs(child, &cs);
+ spibus_get_clock(child, &clockhz);
+ spibus_get_mode(child, &mode);
cs &= ~SPIBUS_CS_HIGH;
@@ -466,6 +468,13 @@ ti_spi_transfer(device_t dev, device_t child, stru
return (EINVAL);
}
+ if (mode > 3)
+ {
+ device_printf(dev, "Invalid mode %d requested by %s\n", mode,
+ device_get_nameunit(child));
+ return (EINVAL);
+ }
+
TI_SPI_LOCK(sc);
/* If the controller is in use wait until it is available. */
@@ -487,8 +496,8 @@ ti_spi_transfer(device_t dev, device_t child, stru
/* Disable FIFO for now. */
sc->sc_fifolvl = 1;
- /* Use a safe clock - 500kHz. */
- ti_spi_set_clock(sc, sc->sc_cs, 500000);
+ /* Set the bus frequency. */
+ ti_spi_set_clock(sc, sc->sc_cs, clockhz);
/* Disable the FIFO. */
TI_SPI_WRITE(sc, MCSPI_XFERLEVEL, 0);
@@ -500,6 +509,7 @@ ti_spi_transfer(device_t dev, device_t child, stru
MCSPI_CONF_DPE1 | MCSPI_CONF_DPE0 | MCSPI_CONF_DMAR |
MCSPI_CONF_DMAW | MCSPI_CONF_EPOL);
reg |= MCSPI_CONF_DPE0 | MCSPI_CONF_EPOL | MCSPI_CONF_WL8BITS;
+ reg |= mode; /* POL and PHA are the low bits, we can just OR-in mode */
TI_SPI_WRITE(sc, MCSPI_CONF_CH(sc->sc_cs), reg);
#if 0
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