Date: Tue, 23 Dec 2008 19:06:33 GMT From: Hans Petter Selasky <hselasky@FreeBSD.org> To: Perforce Change Reviews <perforce@FreeBSD.org> Subject: PERFORCE change 155191 for review Message-ID: <200812231906.mBNJ6XQR026103@repoman.freebsd.org>
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http://perforce.freebsd.org/chv.cgi?CH=155191 Change 155191 by hselasky@hselasky_laptop001 on 2008/12/23 19:05:58 IFC @155167 - final step Integrate if_zyd . Affected files ... .. //depot/projects/usb/src/sys/dev/usb2/wlan/if_zyd2.c#23 edit .. //depot/projects/usb/src/sys/dev/usb2/wlan/if_zyd2_reg.h#8 edit Differences ... ==== //depot/projects/usb/src/sys/dev/usb2/wlan/if_zyd2.c#23 (text+ko) ==== @@ -155,6 +155,7 @@ static void zyd_cfg_amrr_start(struct zyd_softc *); static void zyd_update_mcast_cb(struct ifnet *); static void zyd_update_promisc_cb(struct ifnet *); +static void zyd_cfg_get_macaddr(struct zyd_softc *sc); static const struct zyd_phy_pair zyd_def_phy[] = ZYD_DEF_PHY; static const struct zyd_phy_pair zyd_def_phyB[] = ZYD_DEF_PHYB; @@ -758,7 +759,18 @@ zyd_cfg_cmd(sc, ZYD_CMD_RFCFG, &req, 4 + (2 * rf->width), NULL, 0, 0); } +/*------------------------------------------------------------------------* + * zyd_cfg_rfwrite_cr + *------------------------------------------------------------------------*/ static void +zyd_cfg_rfwrite_cr(struct zyd_softc *sc, uint32_t val) +{ + zyd_cfg_write16(sc, ZYD_CR244, (val >> 16) & 0xff); + zyd_cfg_write16(sc, ZYD_CR243, (val >> 8) & 0xff); + zyd_cfg_write16(sc, ZYD_CR242, (val >> 0) & 0xff); +} + +static void zyd_bulk_read_clear_stall_callback(struct usb2_xfer *xfer) { struct zyd_softc *sc = xfer->priv_sc; @@ -1151,10 +1163,24 @@ static void zyd_cfg_set_beacon_interval(struct zyd_softc *sc, uint32_t bintval) { - /* XXX this is probably broken.. */ - zyd_cfg_write32(sc, ZYD_CR_ATIM_WND_PERIOD, bintval - 2); - zyd_cfg_write32(sc, ZYD_CR_PRE_TBTT, bintval - 1); - zyd_cfg_write32(sc, ZYD_CR_BCN_INTERVAL, bintval); + uint32_t val; + + zyd_cfg_read32(sc, ZYD_CR_ATIM_WND_PERIOD, &val); + sc->sc_atim_wnd = val; + zyd_cfg_read32(sc, ZYD_CR_PRE_TBTT, &val); + sc->sc_pre_tbtt = val; + sc->sc_bcn_int = bintval; + + if (sc->sc_bcn_int <= 5) + sc->sc_bcn_int = 5; + if (sc->sc_pre_tbtt < 4 || sc->sc_pre_tbtt >= sc->sc_bcn_int) + sc->sc_pre_tbtt = sc->sc_bcn_int - 1; + if (sc->sc_atim_wnd >= sc->sc_pre_tbtt) + sc->sc_atim_wnd = sc->sc_pre_tbtt - 1; + + zyd_cfg_write32(sc, ZYD_CR_ATIM_WND_PERIOD, sc->sc_atim_wnd); + zyd_cfg_write32(sc, ZYD_CR_PRE_TBTT, sc->sc_pre_tbtt); + zyd_cfg_write32(sc, ZYD_CR_BCN_INTERVAL, sc->sc_bcn_int); } /* @@ -1166,7 +1192,7 @@ static const char *const zyd_rfs[] = { "unknown", "unknown", "UW2451", "UCHIP", "AL2230", "AL7230B", "THETA", "AL2210", "MAXIM_NEW", "GCT", - "PV2000", "RALINK", "INTERSIL", "RFMD", "MAXIM_NEW2", + "AL2230S", "RALINK", "INTERSIL", "RFMD", "MAXIM_NEW2", "PHILIPS" }; @@ -1238,36 +1264,106 @@ zyd_cfg_rf_al2230_init(struct zyd_softc *sc, struct zyd_rf *rf) { static const struct zyd_phy_pair phyini[] = ZYD_AL2230_PHY; - static const uint32_t rfini[] = ZYD_AL2230_RF; + static const struct zyd_phy_pair phy2230s[] = ZYD_AL2230S_PHY_INIT; + static const struct zyd_phy_pair phypll[] = { + {ZYD_CR251, 0x2f}, {ZYD_CR251, 0x3f}, + {ZYD_CR138, 0x28}, {ZYD_CR203, 0x06} + }; + static const uint32_t rfini1[] = ZYD_AL2230_RF_PART1; + static const uint32_t rfini2[] = ZYD_AL2230_RF_PART2; + static const uint32_t rfini3[] = ZYD_AL2230_RF_PART3; uint32_t i; /* init RF-dependent PHY registers */ - for (i = 0; i != INDEXES(phyini); i++) { + for (i = 0; i != INDEXES(phyini); i++) zyd_cfg_write16(sc, phyini[i].reg, phyini[i].val); + + if ((sc->sc_rf_rev == ZYD_RF_AL2230S) || (sc->sc_al2230s != 0)) { + for (i = 0; i != INDEXES(phy2230s); i++) + zyd_cfg_write16(sc, phy2230s[i].reg, phy2230s[i].val); } + /* init AL2230 radio */ + for (i = 0; i != INDEXES(rfini1); i++) + zyd_cfg_rfwrite(sc, rfini1[i]); + + if ((sc->sc_rf_rev == ZYD_RF_AL2230S) || (sc->sc_al2230s != 0)) + zyd_cfg_rfwrite(sc, 0x000824); + else + zyd_cfg_rfwrite(sc, 0x0005a4); + + for (i = 0; i != INDEXES(rfini2); i++) + zyd_cfg_rfwrite(sc, rfini2[i]); + + for (i = 0; i != INDEXES(phypll); i++) + zyd_cfg_write16(sc, phypll[i].reg, phypll[i].val); + + for (i = 0; i != INDEXES(rfini3); i++) + zyd_cfg_rfwrite(sc, rfini3[i]); +} - /* init AL2230 radio */ - for (i = 0; i != INDEXES(rfini); i++) { - zyd_cfg_rfwrite(sc, rfini[i]); - } +static void +zyd_cfg_rf_al2230_fini(struct zyd_softc *sc, struct zyd_rf *rf) +{ + static const struct zyd_phy_pair phy[] = ZYD_AL2230_PHY_FINI_PART1; + uint32_t i; + + for (i = 0; i != INDEXES(phy); i++) + zyd_cfg_write16(sc, phy[i].reg, phy[i].val); + + if (sc->sc_newphy != 0) + zyd_cfg_write16(sc, ZYD_CR9, 0xe1); + zyd_cfg_write16(sc, ZYD_CR203, 0x6); } static void zyd_cfg_rf_al2230_init_b(struct zyd_softc *sc, struct zyd_rf *rf) { static const struct zyd_phy_pair phyini[] = ZYD_AL2230_PHY_B; - static const uint32_t rfini[] = ZYD_AL2230_RF_B; + static const struct zyd_phy_pair phy1[] = ZYD_AL2230_PHY_PART1; + static const struct zyd_phy_pair phy2[] = ZYD_AL2230_PHY_PART2; + static const struct zyd_phy_pair phy3[] = ZYD_AL2230_PHY_PART3; + static const struct zyd_phy_pair phy2230s[] = ZYD_AL2230S_PHY_INIT; + static const uint32_t rfini_part1[] = ZYD_AL2230_RF_B_PART1; + static const uint32_t rfini_part2[] = ZYD_AL2230_RF_B_PART2; + static const uint32_t rfini_part3[] = ZYD_AL2230_RF_B_PART3; + static const uint32_t zyd_al2230_chtable[][3] = ZYD_AL2230_CHANTABLE; uint32_t i; + for (i = 0; i != INDEXES(phy1); i++) + zyd_cfg_write16(sc, phy1[i].reg, phy1[i].val); + /* init RF-dependent PHY registers */ - for (i = 0; i != INDEXES(phyini); i++) { + for (i = 0; i != INDEXES(phyini); i++) zyd_cfg_write16(sc, phyini[i].reg, phyini[i].val); - } + + if ((sc->sc_rf_rev == ZYD_RF_AL2230S) || (sc->sc_al2230s != 0)) + for (i = 0; i != INDEXES(phy2230s); i++) + zyd_cfg_write16(sc, phy2230s[i].reg, phy2230s[i].val); + + for (i = 0; i != 3; i++) + zyd_cfg_rfwrite_cr(sc, zyd_al2230_chtable[0][i]); + + for (i = 0; i != INDEXES(rfini_part1); i++) + zyd_cfg_rfwrite_cr(sc, rfini_part1[i]); + + if ((sc->sc_rf_rev == ZYD_RF_AL2230S) || (sc->sc_al2230s != 0)) + zyd_cfg_rfwrite(sc, 0x241000); + else + zyd_cfg_rfwrite(sc, 0x25a000); + + for (i = 0; i != INDEXES(rfini_part2); i++) + zyd_cfg_rfwrite_cr(sc, rfini_part2[i]); + + for (i = 0; i != INDEXES(phy2); i++) + zyd_cfg_write16(sc, phy2[i].reg, phy2[i].val); + + for (i = 0; i != INDEXES(rfini_part3); i++) + zyd_cfg_rfwrite_cr(sc, rfini_part3[i]); + + for (i = 0; i < INDEXES(phy3); i++) + zyd_cfg_write16(sc, phy3[i].reg, phy3[i].val); - /* init AL2230 radio */ - for (i = 0; i != INDEXES(rfini); i++) { - zyd_cfg_rfwrite(sc, rfini[i]); - } + zyd_cfg_rf_al2230_fini(sc, rf); } /* @@ -1277,16 +1373,60 @@ zyd_cfg_rf_al2230_set_channel(struct zyd_softc *sc, struct zyd_rf *rf, uint8_t channel) { + static const struct zyd_phy_pair phy1[] = { + {ZYD_CR138, 0x28}, {ZYD_CR203, 0x06}, + }; static const struct { uint32_t r1, r2, r3; } rfprog[] = ZYD_AL2230_CHANTABLE; + uint32_t i; zyd_cfg_rfwrite(sc, rfprog[channel - 1].r1); zyd_cfg_rfwrite(sc, rfprog[channel - 1].r2); zyd_cfg_rfwrite(sc, rfprog[channel - 1].r3); - zyd_cfg_write16(sc, ZYD_CR138, 0x28); - zyd_cfg_write16(sc, ZYD_CR203, 0x06); + for (i = 0; i != INDEXES(phy1); i++) + zyd_cfg_write16(sc, phy1[i].reg, phy1[i].val); +} + +static void +zyd_cfg_rf_al2230_set_channel_b(struct zyd_softc *sc, + struct zyd_rf *rf, uint8_t chan) +{ + static const struct zyd_phy_pair phy1[] = ZYD_AL2230_PHY_PART1; + static const struct { + uint32_t r1, r2, r3; + } rfprog[] = ZYD_AL2230_CHANTABLE_B; + uint32_t i; + + for (i = 0; i != INDEXES(phy1); i++) + zyd_cfg_write16(sc, phy1[i].reg, phy1[i].val); + + zyd_cfg_rfwrite_cr(sc, rfprog[chan - 1].r1); + zyd_cfg_rfwrite_cr(sc, rfprog[chan - 1].r2); + zyd_cfg_rfwrite_cr(sc, rfprog[chan - 1].r3); + + zyd_cfg_rf_al2230_fini(sc, rf); +} + +#define ZYD_AL2230_PHY_BANDEDGE6 \ +{ \ + { ZYD_CR128, 0x14 }, { ZYD_CR129, 0x12 }, { ZYD_CR130, 0x10 }, \ + { ZYD_CR47, 0x1e } \ +} + +static void +zyd_cfg_rf_al2230_bandedge6(struct zyd_softc *sc, + struct zyd_rf *rf, uint8_t chan) +{ + struct zyd_phy_pair r[] = ZYD_AL2230_PHY_BANDEDGE6; + uint32_t i; + + if ((chan == 1) || (chan == 11)) + r[0].val = 0x12; + + for (i = 0; i < INDEXES(r); i++) + zyd_cfg_write16(sc, r[i].reg, r[i].val); } /* @@ -1416,7 +1556,6 @@ zyd_cfg_write32(sc, ZYD_CR_RADIO_PD, tmp & ~1); zyd_cfg_write32(sc, ZYD_CR_RADIO_PD, tmp | 1); zyd_cfg_write32(sc, ZYD_CR_RFCFG, 0x05); - zyd_cfg_write32(sc, ZYD_CR_RFCFG, 0x00); zyd_cfg_write16(sc, ZYD_CR47, 0x1e); @@ -1620,12 +1759,16 @@ rf->width = 24; /* 24-bit RF values */ break; case ZYD_RF_AL2230: - if (sc->sc_mac_rev == ZYD_ZD1211B) + case ZYD_RF_AL2230S: + if (sc->sc_mac_rev == ZYD_ZD1211B) { rf->cfg_init_hw = zyd_cfg_rf_al2230_init_b; - else + rf->cfg_set_channel = zyd_cfg_rf_al2230_set_channel_b; + } else { rf->cfg_init_hw = zyd_cfg_rf_al2230_init; + rf->cfg_set_channel = zyd_cfg_rf_al2230_set_channel; + } rf->cfg_switch_radio = zyd_cfg_rf_al2230_switch_radio; - rf->cfg_set_channel = zyd_cfg_rf_al2230_set_channel; + rf->cfg_bandedge6 = zyd_cfg_rf_al2230_bandedge6; rf->width = 24; /* 24-bit RF values */ break; case ZYD_RF_AL7230B: @@ -1692,6 +1835,9 @@ zyd_cfg_write32(sc, ZYD_CR_GPI_EN, 0); zyd_cfg_write32(sc, ZYD_MAC_CONT_WIN_LIMIT, 0x7f043f); + /* set mandatory rates - XXX assumes 802.11b/g */ + zyd_cfg_write32(sc, ZYD_MAC_MAN_RATE, 0x150f); + /* disable interrupts */ zyd_cfg_write32(sc, ZYD_CR_INTERRUPT, 0); @@ -1701,7 +1847,7 @@ for (; phyp->reg != 0; phyp++) { zyd_cfg_write16(sc, phyp->reg, phyp->val); } - if (sc->sc_fix_cr157) { + if ((sc->sc_mac_rev == ZYD_ZD1211) && sc->sc_fix_cr157) { zyd_cfg_read32(sc, ZYD_EEPROM_PHY_REG, &tmp); zyd_cfg_write32(sc, ZYD_CR157, tmp >> 8); } @@ -1710,20 +1856,6 @@ /* HMAC init */ zyd_cfg_write32(sc, ZYD_MAC_ACK_EXT, 0x00000020); zyd_cfg_write32(sc, ZYD_CR_ADDA_MBIAS_WT, 0x30000808); - - if (sc->sc_mac_rev == ZYD_ZD1211) { - zyd_cfg_write32(sc, ZYD_MAC_RETRY, 0x00000002); - } else { - zyd_cfg_write32(sc, ZYD_MACB_MAX_RETRY, 0x02020202); - zyd_cfg_write32(sc, ZYD_MACB_TXPWR_CTL4, 0x007f003f); - zyd_cfg_write32(sc, ZYD_MACB_TXPWR_CTL3, 0x007f003f); - zyd_cfg_write32(sc, ZYD_MACB_TXPWR_CTL2, 0x003f001f); - zyd_cfg_write32(sc, ZYD_MACB_TXPWR_CTL1, 0x001f000f); - zyd_cfg_write32(sc, ZYD_MACB_AIFS_CTL1, 0x00280028); - zyd_cfg_write32(sc, ZYD_MACB_AIFS_CTL2, 0x008C003C); - zyd_cfg_write32(sc, ZYD_MACB_TXOP, 0x01800824); - } - zyd_cfg_write32(sc, ZYD_MAC_SNIFFER, 0x00000000); zyd_cfg_write32(sc, ZYD_MAC_RXFILTER, 0x00000000); zyd_cfg_write32(sc, ZYD_MAC_GHTBL, 0x00000000); @@ -1735,12 +1867,28 @@ zyd_cfg_write32(sc, ZYD_MAC_ACK_EXT, 0x00000080); zyd_cfg_write32(sc, ZYD_CR_ADDA_PWR_DWN, 0x00000000); zyd_cfg_write32(sc, ZYD_MAC_SIFS_ACK_TIME, 0x00000100); - zyd_cfg_write32(sc, ZYD_MAC_DIFS_EIFS_SIFS, 0x0547c032); zyd_cfg_write32(sc, ZYD_CR_RX_PE_DELAY, 0x00000070); zyd_cfg_write32(sc, ZYD_CR_PS_CTRL, 0x10000000); zyd_cfg_write32(sc, ZYD_MAC_RTSCTSRATE, 0x02030203); - zyd_cfg_write32(sc, ZYD_MAC_RX_THRESHOLD, 0x000c0640); + zyd_cfg_write32(sc, ZYD_MAC_AFTER_PNP, 1); zyd_cfg_write32(sc, ZYD_MAC_BACKOFF_PROTECT, 0x00000114); + zyd_cfg_write32(sc, ZYD_MAC_DIFS_EIFS_SIFS, 0x0a47c032); + zyd_cfg_write32(sc, ZYD_MAC_CAM_MODE, 0x3); + + if (sc->sc_mac_rev == ZYD_ZD1211) { + zyd_cfg_write32(sc, ZYD_MAC_RETRY, 0x00000002); + zyd_cfg_write32(sc, ZYD_MAC_RX_THRESHOLD, 0x000c0640); + } else { + zyd_cfg_write32(sc, ZYD_MACB_MAX_RETRY, 0x02020202); + zyd_cfg_write32(sc, ZYD_MACB_TXPWR_CTL4, 0x007f003f); + zyd_cfg_write32(sc, ZYD_MACB_TXPWR_CTL3, 0x007f003f); + zyd_cfg_write32(sc, ZYD_MACB_TXPWR_CTL2, 0x003f001f); + zyd_cfg_write32(sc, ZYD_MACB_TXPWR_CTL1, 0x001f000f); + zyd_cfg_write32(sc, ZYD_MACB_AIFS_CTL1, 0x00280028); + zyd_cfg_write32(sc, ZYD_MACB_AIFS_CTL2, 0x008C003C); + zyd_cfg_write32(sc, ZYD_MACB_TXOP, 0x01800824); + zyd_cfg_write32(sc, ZYD_MAC_RX_THRESHOLD, 0x000c0eff); + } /* init beacon interval to 100ms */ zyd_cfg_set_beacon_interval(sc, 100); @@ -1759,20 +1907,19 @@ uint16_t val; /* read MAC address */ - zyd_cfg_read32(sc, ZYD_EEPROM_MAC_ADDR_P1, &tmp); - sc->sc_myaddr[0] = tmp & 0xff; - sc->sc_myaddr[1] = tmp >> 8; - sc->sc_myaddr[2] = tmp >> 16; - sc->sc_myaddr[3] = tmp >> 24; - zyd_cfg_read32(sc, ZYD_EEPROM_MAC_ADDR_P2, &tmp); - sc->sc_myaddr[4] = tmp & 0xff; - sc->sc_myaddr[5] = tmp >> 8; + zyd_cfg_get_macaddr(sc); + /* read product data */ zyd_cfg_read32(sc, ZYD_EEPROM_POD, &tmp); sc->sc_rf_rev = tmp & 0x0f; - sc->sc_fix_cr47 = (tmp >> 8) & 0x01; + sc->sc_ledtype = (tmp >> 4) & 0x01; + sc->sc_cckgain = (tmp >> 8) & 0x01; sc->sc_fix_cr157 = (tmp >> 13) & 0x01; sc->sc_pa_rev = (tmp >> 16) & 0x0f; + sc->sc_al2230s = (tmp >> 7) & 0x01; + sc->sc_bandedge6 = (tmp >> 21) & 0x01; + sc->sc_newphy = (tmp >> 31) & 0x01; + sc->sc_txled = ((tmp & (1 << 24)) && (tmp & (1 << 29))) ? 0 : 1; /* read regulatory domain (currently unused) */ zyd_cfg_read32(sc, ZYD_EEPROM_SUBID, &tmp); @@ -1804,6 +1951,21 @@ } static void +zyd_cfg_get_macaddr(struct zyd_softc *sc) +{ + struct usb2_device_request req; + + req.bmRequestType = UT_READ_VENDOR_DEVICE; + req.bRequest = ZYD_READFWDATAREQ; + USETW(req.wValue, ZYD_EEPROM_MAC_ADDR_P1); + USETW(req.wIndex, 0); + USETW(req.wLength, IEEE80211_ADDR_LEN); + + zyd_cfg_usbrequest(sc, &req, sc->sc_myaddr); + return; +} + +static void zyd_cfg_set_mac_addr(struct zyd_softc *sc, const uint8_t *addr) { uint32_t tmp; @@ -2273,17 +2435,18 @@ zyd_cfg_write16(sc, ZYD_CR67, sc->sc_ofdm36_cal[chan - 1]); zyd_cfg_write16(sc, ZYD_CR66, sc->sc_ofdm48_cal[chan - 1]); zyd_cfg_write16(sc, ZYD_CR65, sc->sc_ofdm54_cal[chan - 1]); - zyd_cfg_write16(sc, ZYD_CR68, sc->sc_pwr_cal[chan - 1]); - zyd_cfg_write16(sc, ZYD_CR69, 0x28); zyd_cfg_write16(sc, ZYD_CR69, 0x2a); } - if (sc->sc_fix_cr47) { + if (sc->sc_cckgain) { /* set CCK baseband gain from EEPROM */ zyd_cfg_read32(sc, ZYD_EEPROM_PHY_REG, &tmp); zyd_cfg_write16(sc, ZYD_CR47, tmp & 0xff); } + if (sc->sc_bandedge6 && (sc->sc_rf.cfg_bandedge6 != NULL)) { + (sc->sc_rf.cfg_bandedge6) (sc, &sc->sc_rf, chan); + } zyd_cfg_write32(sc, ZYD_CR_CONFIG_PHILIPS, 0); zyd_cfg_unlock_phy(sc); @@ -2352,7 +2515,7 @@ else if (cc->ic_curmode == IEEE80211_MODE_11A) zyd_cfg_write32(sc, ZYD_MAC_BAS_RATE, 0x1500); else /* assumes 802.11b/g */ - zyd_cfg_write32(sc, ZYD_MAC_BAS_RATE, 0x000f); + zyd_cfg_write32(sc, ZYD_MAC_BAS_RATE, 0xff0f); /* set mandatory rates */ if (cc->ic_curmode == IEEE80211_MODE_11B) ==== //depot/projects/usb/src/sys/dev/usb2/wlan/if_zyd2_reg.h#8 (text+ko) ==== @@ -101,6 +101,7 @@ #define ZYD_MAC_CONT_WIN_LIMIT 0x96f0 /* Contention window limit */ #define ZYD_MAC_TX_PKT 0x96f4 /* Tx total packet count read */ #define ZYD_MAC_DL_CTRL 0x96f8 /* Download control */ +#define ZYD_MAC_CAM_MODE 0x9700 /* CAM: Continuous Access Mode */ #define ZYD_MACB_TXPWR_CTL1 0x9b00 #define ZYD_MACB_TXPWR_CTL2 0x9b04 #define ZYD_MACB_TXPWR_CTL3 0x9b08 @@ -127,8 +128,8 @@ #define ZYD_EEPROM_PWR_CAL 0xf81f /* Calibration */ #define ZYD_EEPROM_PWR_INT 0xf827 /* Calibration */ #define ZYD_EEPROM_ALLOWEDCHAN 0xf82f /* Allowed CH mask, 1 bit each */ -#define ZYD_EEPROM_PHY_REG 0xf831 /* PHY registers */ #define ZYD_EEPROM_DEVICE_VER 0xf837 /* Device version */ +#define ZYD_EEPROM_PHY_REG 0xf83c /* PHY registers */ #define ZYD_EEPROM_36M_CAL 0xf83f /* Calibration */ #define ZYD_EEPROM_11A_INT 0xf847 /* Interpolation */ #define ZYD_EEPROM_48M_CAL 0xf84f /* Calibration */ @@ -161,7 +162,7 @@ #define ZYD_RF_AL2210 0x7 #define ZYD_RF_MAXIM_NEW 0x8 #define ZYD_RF_GCT 0x9 -#define ZYD_RF_PV2000 0xa /* not supported yet */ +#define ZYD_RF_AL2230S 0xa #define ZYD_RF_RALINK 0xb /* not supported yet */ #define ZYD_RF_INTERSIL 0xc /* not supported yet */ #define ZYD_RF_RFMD 0xd @@ -437,7 +438,7 @@ { ZYD_CR37, 0x00 }, { ZYD_CR38, 0x38 }, { ZYD_CR39, 0x0c }, \ { ZYD_CR40, 0x84 }, { ZYD_CR41, 0x2a }, { ZYD_CR42, 0x80 }, \ { ZYD_CR43, 0x10 }, { ZYD_CR44, 0x12 }, { ZYD_CR46, 0xff }, \ - { ZYD_CR47, 0x08 }, { ZYD_CR48, 0x26 }, { ZYD_CR49, 0x5b }, \ + { ZYD_CR47, 0x1e }, { ZYD_CR48, 0x26 }, { ZYD_CR49, 0x5b }, \ { ZYD_CR64, 0xd0 }, { ZYD_CR65, 0x04 }, { ZYD_CR66, 0x58 }, \ { ZYD_CR67, 0xc9 }, { ZYD_CR68, 0x88 }, { ZYD_CR69, 0x41 }, \ { ZYD_CR70, 0x23 }, { ZYD_CR71, 0x10 }, { ZYD_CR72, 0xff }, \ @@ -459,7 +460,7 @@ { ZYD_CR5, 0x00 }, { ZYD_CR6, 0x00 }, { ZYD_CR7, 0x00 }, \ { ZYD_CR8, 0x00 }, { ZYD_CR9, 0x20 }, { ZYD_CR12, 0xf0 }, \ { ZYD_CR20, 0x0e }, { ZYD_CR21, 0x0e }, { ZYD_CR27, 0x10 }, \ - { ZYD_CR44, 0x33 }, { ZYD_CR47, 0x30 }, { ZYD_CR83, 0x24 }, \ + { ZYD_CR44, 0x33 }, { ZYD_CR47, 0x1E }, { ZYD_CR83, 0x24 }, \ { ZYD_CR84, 0x04 }, { ZYD_CR85, 0x00 }, { ZYD_CR86, 0x0C }, \ { ZYD_CR87, 0x12 }, { ZYD_CR88, 0x0C }, { ZYD_CR89, 0x00 }, \ { ZYD_CR90, 0x10 }, { ZYD_CR91, 0x08 }, { ZYD_CR93, 0x00 }, \ @@ -470,19 +471,18 @@ { ZYD_CR111, 0x27 }, { ZYD_CR112, 0x27 }, { ZYD_CR113, 0x27 }, \ { ZYD_CR114, 0x27 }, { ZYD_CR115, 0x26 }, { ZYD_CR116, 0x24 }, \ { ZYD_CR117, 0xfc }, { ZYD_CR118, 0xfa }, { ZYD_CR120, 0x4f }, \ - { ZYD_CR123, 0x27 }, { ZYD_CR125, 0xaa }, { ZYD_CR127, 0x03 }, \ - { ZYD_CR128, 0x14 }, { ZYD_CR129, 0x12 }, { ZYD_CR130, 0x10 }, \ - { ZYD_CR131, 0x0C }, { ZYD_CR136, 0xdf }, { ZYD_CR137, 0x40 }, \ - { ZYD_CR138, 0xa0 }, { ZYD_CR139, 0xb0 }, { ZYD_CR140, 0x99 }, \ - { ZYD_CR141, 0x82 }, { ZYD_CR142, 0x54 }, { ZYD_CR143, 0x1c }, \ - { ZYD_CR144, 0x6c }, { ZYD_CR147, 0x07 }, { ZYD_CR148, 0x4c }, \ - { ZYD_CR149, 0x50 }, { ZYD_CR150, 0x0e }, { ZYD_CR151, 0x18 }, \ - { ZYD_CR160, 0xfe }, { ZYD_CR161, 0xee }, { ZYD_CR162, 0xaa }, \ - { ZYD_CR163, 0xfa }, { ZYD_CR164, 0xfa }, { ZYD_CR165, 0xea }, \ - { ZYD_CR166, 0xbe }, { ZYD_CR167, 0xbe }, { ZYD_CR168, 0x6a }, \ - { ZYD_CR169, 0xba }, { ZYD_CR170, 0xba }, { ZYD_CR171, 0xba }, \ - { ZYD_CR204, 0x7d }, { ZYD_CR203, 0x30 }, \ - { 0, 0 } \ + { ZYD_CR125, 0xaa }, { ZYD_CR127, 0x03 }, { ZYD_CR128, 0x14 }, \ + { ZYD_CR129, 0x12 }, { ZYD_CR130, 0x10 }, { ZYD_CR131, 0x0C }, \ + { ZYD_CR136, 0xdf }, { ZYD_CR137, 0x40 }, { ZYD_CR138, 0xa0 }, \ + { ZYD_CR139, 0xb0 }, { ZYD_CR140, 0x99 }, { ZYD_CR141, 0x82 }, \ + { ZYD_CR142, 0x54 }, { ZYD_CR143, 0x1c }, { ZYD_CR144, 0x6c }, \ + { ZYD_CR147, 0x07 }, { ZYD_CR148, 0x4c }, { ZYD_CR149, 0x50 }, \ + { ZYD_CR150, 0x0e }, { ZYD_CR151, 0x18 }, { ZYD_CR160, 0xfe }, \ + { ZYD_CR161, 0xee }, { ZYD_CR162, 0xaa }, { ZYD_CR163, 0xfa }, \ + { ZYD_CR164, 0xfa }, { ZYD_CR165, 0xea }, { ZYD_CR166, 0xbe }, \ + { ZYD_CR167, 0xbe }, { ZYD_CR168, 0x6a }, { ZYD_CR169, 0xba }, \ + { ZYD_CR170, 0xba }, { ZYD_CR171, 0xba }, { ZYD_CR204, 0x7d }, \ + { ZYD_CR203, 0x30 }, { 0, 0} \ } #define ZYD_DEF_PHYB \ @@ -590,8 +590,6 @@ { 0x181a60, 0x1c0000 } \ } - - #define ZYD_AL2230_PHY \ { \ { ZYD_CR15, 0x20 }, { ZYD_CR23, 0x40 }, { ZYD_CR24, 0x20 }, \ @@ -617,34 +615,73 @@ #define ZYD_AL2230_PHY_B \ { \ - { ZYD_CR10, 0x89 }, { ZYD_CR15, 0x20 }, { ZYD_CR17, 0x2b }, \ + { ZYD_CR10, 0x89 }, { ZYD_CR15, 0x20 }, { ZYD_CR17, 0x2B }, \ { ZYD_CR23, 0x40 }, { ZYD_CR24, 0x20 }, { ZYD_CR26, 0x93 }, \ { ZYD_CR28, 0x3e }, { ZYD_CR29, 0x00 }, { ZYD_CR33, 0x28 }, \ { ZYD_CR34, 0x30 }, { ZYD_CR35, 0x3e }, { ZYD_CR41, 0x24 }, \ { ZYD_CR44, 0x32 }, { ZYD_CR46, 0x99 }, { ZYD_CR47, 0x1e }, \ - { ZYD_CR48, 0x00 }, { ZYD_CR49, 0x00 }, { ZYD_CR51, 0x01 }, \ + { ZYD_CR48, 0x06 }, { ZYD_CR49, 0xf9 }, { ZYD_CR51, 0x01 }, \ { ZYD_CR52, 0x80 }, { ZYD_CR53, 0x7e }, { ZYD_CR65, 0x00 }, \ { ZYD_CR66, 0x00 }, { ZYD_CR67, 0x00 }, { ZYD_CR68, 0x00 }, \ { ZYD_CR69, 0x28 }, { ZYD_CR79, 0x58 }, { ZYD_CR80, 0x30 }, \ { ZYD_CR81, 0x30 }, { ZYD_CR87, 0x0a }, { ZYD_CR89, 0x04 }, \ { ZYD_CR91, 0x00 }, { ZYD_CR92, 0x0a }, { ZYD_CR98, 0x8d }, \ - { ZYD_CR99, 0x00 }, { ZYD_CR101, 0x13 }, { ZYD_CR106, 0x24 }, \ - { ZYD_CR107, 0x2a }, { ZYD_CR109, 0x13 }, { ZYD_CR110, 0x1f }, \ - { ZYD_CR111, 0x1f }, { ZYD_CR114, 0x27 }, { ZYD_CR115, 0x26 }, \ + { ZYD_CR99, 0x00 }, { ZYD_CR101, 0x13 }, { ZYD_CR102, 0x27 }, \ + { ZYD_CR106, 0x24 }, { ZYD_CR107, 0x2a }, { ZYD_CR109, 0x13 }, \ + { ZYD_CR110, 0x1f }, { ZYD_CR111, 0x1f }, { ZYD_CR112, 0x1f }, \ + { ZYD_CR113, 0x27 }, { ZYD_CR114, 0x27 }, { ZYD_CR115, 0x26 }, \ { ZYD_CR116, 0x24 }, { ZYD_CR117, 0xfa }, { ZYD_CR118, 0xfa }, \ { ZYD_CR119, 0x10 }, { ZYD_CR120, 0x4f }, { ZYD_CR121, 0x6c }, \ { ZYD_CR122, 0xfc }, { ZYD_CR123, 0x57 }, { ZYD_CR125, 0xad }, \ { ZYD_CR126, 0x6c }, { ZYD_CR127, 0x03 }, { ZYD_CR137, 0x50 }, \ { ZYD_CR138, 0xa8 }, { ZYD_CR144, 0xac }, { ZYD_CR150, 0x0d }, \ - { ZYD_CR252, 0x00 }, { ZYD_CR253, 0x00 } \ + { ZYD_CR252, 0x34 }, { ZYD_CR253, 0x34 } \ +} + +#define ZYD_AL2230_PHY_PART1 \ +{ \ + { ZYD_CR240, 0x57 }, { ZYD_CR9, 0xe0 } \ +} + +#define ZYD_AL2230_PHY_PART2 \ +{ \ + { ZYD_CR251, 0x2f }, { ZYD_CR251, 0x7f }, \ +} + +#define ZYD_AL2230_PHY_PART3 \ +{ \ + { ZYD_CR128, 0x14 }, { ZYD_CR129, 0x12 }, { ZYD_CR130, 0x10 }, \ +} + +#define ZYD_AL2230S_PHY_INIT \ +{ \ + { ZYD_CR47, 0x1e }, { ZYD_CR106, 0x22 }, { ZYD_CR107, 0x2a }, \ + { ZYD_CR109, 0x13 }, { ZYD_CR118, 0xf8 }, { ZYD_CR119, 0x12 }, \ + { ZYD_CR122, 0xe0 }, { ZYD_CR128, 0x10 }, { ZYD_CR129, 0x0e }, \ + { ZYD_CR130, 0x10 } \ +} + +#define ZYD_AL2230_PHY_FINI_PART1 \ +{ \ + { ZYD_CR80, 0x30 }, { ZYD_CR81, 0x30 }, { ZYD_CR79, 0x58 }, \ + { ZYD_CR12, 0xf0 }, { ZYD_CR77, 0x1b }, { ZYD_CR78, 0x58 }, \ + { ZYD_CR203, 0x06 }, { ZYD_CR240, 0x80 }, \ +} + +#define ZYD_AL2230_RF_PART1 \ +{ \ + 0x03f790, 0x033331, 0x00000d, 0x0b3331, 0x03b812, 0x00fff3 \ } -#define ZYD_AL2230_RF \ +#define ZYD_AL2230_RF_PART2 \ { \ - 0x03f790, 0x033331, 0x00000d, 0x0b3331, 0x03b812, 0x00fff3, \ 0x000da4, 0x0f4dc5, 0x0805b6, 0x011687, 0x000688, 0x0403b9, \ - 0x00dbba, 0x00099b, 0x0bdffc, 0x00000d, 0x00500f, 0x00d00f, \ - 0x004c0f, 0x00540f, 0x00700f, 0x00500f \ + 0x00dbba, 0x00099b, 0x0bdffc, 0x00000d, 0x00500f \ +} + +#define ZYD_AL2230_RF_PART3 \ +{ \ + 0x00d00f, 0x004c0f, 0x00540f, 0x00700f, 0x00500f \ } #define ZYD_AL2230_RF_B \ @@ -654,6 +691,22 @@ 0x00dbba, 0x00099b, 0x0bdffc, 0x00000d, 0x00580f \ } +#define ZYD_AL2230_RF_B_PART1 \ +{ \ + 0x8cccd0, 0x481dc0, 0xcfff00, 0x25a000 \ +} + +#define ZYD_AL2230_RF_B_PART2 \ +{ \ + 0x25a000, 0xa3b2f0, 0x6da010, 0xe36280, 0x116000, 0x9dc020, \ + 0x5ddb00, 0xd99000, 0x3ffbd0, 0xb00000, 0xf01a00 \ +} + +#define ZYD_AL2230_RF_B_PART3 \ +{ \ + 0xf01b00, 0xf01e00, 0xf01a00 \ +} + #define ZYD_AL2230_CHANTABLE \ { \ { 0x03f790, 0x033331, 0x00000d }, \ @@ -672,7 +725,23 @@ { 0x03e7c0, 0x066661, 0x00000d } \ } - +#define ZYD_AL2230_CHANTABLE_B \ +{ \ + { 0x09efc0, 0x8cccc0, 0xb00000 }, \ + { 0x09efc0, 0x8cccd0, 0xb00000 }, \ + { 0x09e7c0, 0x8cccc0, 0xb00000 }, \ + { 0x09e7c0, 0x8cccd0, 0xb00000 }, \ + { 0x05efc0, 0x8cccc0, 0xb00000 }, \ + { 0x05efc0, 0x8cccd0, 0xb00000 }, \ + { 0x05e7c0, 0x8cccc0, 0xb00000 }, \ + { 0x05e7c0, 0x8cccd0, 0xb00000 }, \ + { 0x0defc0, 0x8cccc0, 0xb00000 }, \ + { 0x0defc0, 0x8cccd0, 0xb00000 }, \ + { 0x0de7c0, 0x8cccc0, 0xb00000 }, \ + { 0x0de7c0, 0x8cccd0, 0xb00000 }, \ + { 0x03efc0, 0x8cccc0, 0xb00000 }, \ + { 0x03e7c0, 0x866660, 0xb00000 } \ +} #define ZYD_AL7230B_PHY_1 \ { \ @@ -744,8 +813,6 @@ { 0x03ec00, 0x866660 } \ } - - #define ZYD_AL2210_PHY \ { \ { ZYD_CR9, 0xe0 }, { ZYD_CR10, 0x91 }, { ZYD_CR12, 0x90 }, \ @@ -771,8 +838,6 @@ 0x019a80, 0x019b40 \ } - - #define ZYD_GCT_PHY \ { \ { ZYD_CR47, 0x1e }, { ZYD_CR15, 0xdc }, { ZYD_CR113, 0xc0 }, \ @@ -801,8 +866,6 @@ 0x1a3000, 0x1ab000 \ } - - #define ZYD_MAXIM_PHY \ { \ { ZYD_CR23, 0x40 }, { ZYD_CR15, 0x20 }, { ZYD_CR28, 0x3e }, \ @@ -855,8 +918,6 @@ { 0x199a4, 0x20a53 } \ } - - #define ZYD_MAXIM2_PHY \ { \ { ZYD_CR23, 0x40 }, { ZYD_CR15, 0x20 }, { ZYD_CR28, 0x3e }, \ @@ -919,6 +980,7 @@ */ #define ZYD_DOWNLOADREQ 0x30 #define ZYD_DOWNLOADSTS 0x31 +#define ZYD_READFWDATAREQ 0x32 /* possible values for register ZYD_CR_INTERRUPT */ #define ZYD_HWINT_MASK 0x004f0000 @@ -950,10 +1012,15 @@ /* helpers for register ZYD_MAC_RXFILTER */ #define ZYD_FILTER_MONITOR 0xffffffff -#define ZYD_FILTER_BSS \ - (ZYD_FILTER_ASS_RSP | ZYD_FILTER_REASS_RSP | \ - ZYD_FILTER_PRB_RSP | ZYD_FILTER_BCN | ZYD_FILTER_DEASS | \ - ZYD_FILTER_AUTH | ZYD_FILTER_DEAUTH) +#define ZYD_FILTER_BSS \ + (ZYD_FILTER_ASS_REQ | ZYD_FILTER_ASS_RSP | \ + ZYD_FILTER_REASS_REQ | ZYD_FILTER_REASS_RSP | \ + ZYD_FILTER_PRB_REQ | ZYD_FILTER_PRB_RSP | \ + (0x3 << 6) | \ + ZYD_FILTER_BCN | ZYD_FILTER_ATIM | ZYD_FILTER_DEASS | \ + ZYD_FILTER_AUTH | ZYD_FILTER_DEAUTH | \ + (0x7 << 13) | \ + ZYD_FILTER_PS_POLL | ZYD_FILTER_ACK) #define ZYD_FILTER_HOSTAP \ (ZYD_FILTER_ASS_REQ | ZYD_FILTER_REASS_REQ | \ ZYD_FILTER_PRB_REQ | ZYD_FILTER_DEASS | ZYD_FILTER_AUTH | \ @@ -1138,6 +1205,8 @@ void (*cfg_init_hw) (struct zyd_softc *, struct zyd_rf *); void (*cfg_switch_radio) (struct zyd_softc *, uint8_t on); void (*cfg_set_channel) (struct zyd_softc *, struct zyd_rf *, uint8_t); + void (*cfg_bandedge6) (struct zyd_softc *, struct zyd_rf *, uint8_t); + uint8_t width; }; @@ -1239,6 +1308,10 @@ uint32_t sc_rxtap_len; uint32_t sc_txtap_len; uint32_t sc_unit; + uint32_t sc_atim_wnd; + uint32_t sc_pre_tbtt; + uint32_t sc_bcn_int; + int sc_ns_arg; uint16_t sc_firmware_base; @@ -1254,7 +1327,12 @@ uint8_t sc_mac_rev; uint8_t sc_rf_rev; uint8_t sc_pa_rev; - uint8_t sc_fix_cr47; + uint8_t sc_al2230s; + uint8_t sc_cckgain; + uint8_t sc_bandedge6; + uint8_t sc_newphy; + uint8_t sc_ledtype; + uint8_t sc_txled; uint8_t sc_fix_cr157; uint8_t sc_pwr_cal[14]; uint8_t sc_pwr_int[14];
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