From owner-svn-src-all@freebsd.org Tue Dec 11 00:58:23 2018 Return-Path: Delivered-To: svn-src-all@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id 789CD130B3F4 for ; Tue, 11 Dec 2018 00:58:23 +0000 (UTC) (envelope-from kevin.bowling@kev009.com) Received: from mail-io1-xd41.google.com (mail-io1-xd41.google.com [IPv6:2607:f8b0:4864:20::d41]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (Client CN "smtp.gmail.com", Issuer "Google Internet Authority G3" (verified OK)) by mx1.freebsd.org (Postfix) with ESMTPS id C4B6577902 for ; Tue, 11 Dec 2018 00:58:22 +0000 (UTC) (envelope-from kevin.bowling@kev009.com) Received: by mail-io1-xd41.google.com with SMTP id k7so10419630iob.6 for ; Mon, 10 Dec 2018 16:58:22 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kev009.com; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=8RPg+MrYZVuBBbyFjwSZ9Y2OH8NP5U0j4CpG9ScyM7o=; b=iGQH1QJrAGY/W2W7VKkEO9C280MHu9k6MnX6Z1nJduvSWYCpSFEOEoPDUCZ8s0dEnV 7P+gOmdBHCyPEOLI/p919cHoy1cqZ9/jaFu47WHhyEPqFRh6f+y2TvbGv72pzfYw4jfb 51K6U2fzJeCCIrTxhNqHm7QL1fYith+5ujags= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=8RPg+MrYZVuBBbyFjwSZ9Y2OH8NP5U0j4CpG9ScyM7o=; b=PLKdWGB3JN1kYFnfgdG6Ngw8lztrG6agIR9d5bmd3UirX877k/vxVpeZq6xPCp8Kwe 0Z+sEg6dF1n7Bl9ROVygsSv7OareTajUEEhInNoaRNdng1q+FcHzpjAXisaLh0HVDF91 pe5M6s76m0jvX2cw+nOCOfQ71TqTdSmcl2+6T4Qpm7DJBc9hWcX/13n1DbEAZf8THpv+ IryNrhje2hQYGhgKJ3Go3ERkHdr/qpLKQqLFEOi6Uv5QtBr7V+5pN/hwGgHEkZH92GbI 9qclvRu02uIqyF4ZUEfBJE+ruAl3Nm94FzmPjtQS4lFx3+BpJajxXECvQLUXnaG5szoh hL0g== X-Gm-Message-State: AA+aEWZs7ABn6i7/qkTth2vhAC3woIAmzBzD2AVREnnaMMTzltU24qQ6 8xwQuD//th8e8LdZnE5y9n7VXGytCjMXRqHsvYsoFg== X-Google-Smtp-Source: AFSGD/WWC8UKjaEjmPZUq+bsxIEObABl3PF4lK/6IZ2gMwKzaa8vhtECpe/1bVF0sFFOVFoVjLQroLW1+5GI/4GjKDY= X-Received: by 2002:a5d:9654:: with SMTP id d20mr11691159ios.257.1544489902143; Mon, 10 Dec 2018 16:58:22 -0800 (PST) MIME-Version: 1.0 References: <201812071205.wB7C5BvA038350@repo.freebsd.org> <1544206201.1860.288.camel@freebsd.org> <45f85061-2633-852c-3cc0-41f64d51e4f0@FreeBSD.org> <1544486233.1860.343.camel@freebsd.org> In-Reply-To: From: Kevin Bowling Date: Mon, 10 Dec 2018 17:58:10 -0700 Message-ID: Subject: Re: svn commit: r341682 - head/sys/sys To: Justin Hibbits Cc: ian@freebsd.org, John Baldwin , Warner Losh , mjguzik@gmail.com, svn-src-head@freebsd.org, svn-src-all@freebsd.org, src-committers , scottl@freebsd.org Content-Type: text/plain; charset="UTF-8" X-Rspamd-Queue-Id: C4B6577902 X-Spamd-Result: default: False [0.95 / 15.00]; ARC_NA(0.00)[]; FROM_HAS_DN(0.00)[]; TO_DN_SOME(0.00)[]; R_SPF_ALLOW(-0.20)[+ip6:2607:f8b0:4000::/36]; NEURAL_HAM_LONG(-0.05)[-0.054,0]; MIME_GOOD(-0.10)[text/plain]; PREVIOUSLY_DELIVERED(0.00)[svn-src-all@freebsd.org]; DMARC_NA(0.00)[kev009.com]; NEURAL_SPAM_MEDIUM(0.52)[0.515,0]; NEURAL_SPAM_SHORT(0.62)[0.615,0]; TO_MATCH_ENVRCPT_SOME(0.00)[]; DKIM_TRACE(0.00)[kev009.com:~]; MX_GOOD(-0.01)[cached: alt1.aspmx.l.google.com]; RCPT_COUNT_SEVEN(0.00)[9]; RCVD_IN_DNSWL_NONE(0.00)[1.4.d.0.0.0.0.0.0.0.0.0.0.0.0.0.0.2.0.0.4.6.8.4.0.b.8.f.7.0.6.2.list.dnswl.org : 127.0.5.0]; R_DKIM_PERMFAIL(0.00)[kev009.com]; FREEMAIL_TO(0.00)[gmail.com]; FROM_EQ_ENVFROM(0.00)[]; RCVD_TLS_LAST(0.00)[]; IP_SCORE(0.18)[ip: (3.78), ipnet: 2607:f8b0::/32(-1.52), asn: 15169(-1.27), country: US(-0.09)]; ASN(0.00)[asn:15169, ipnet:2607:f8b0::/32, country:US]; RCVD_COUNT_TWO(0.00)[2] X-Rspamd-Server: mx1.freebsd.org X-BeenThere: svn-src-all@freebsd.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: "SVN commit messages for the entire src tree \(except for " user" and " projects" \)" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 11 Dec 2018 00:58:23 -0000 Humor me with a kernel feature that will sue 64b atomics while both instruction streams are ping ponging on the hypothetical lock because this thread is getting pretty far out there.. On Mon, Dec 10, 2018 at 5:27 PM Justin Hibbits wrote: > > > > On Mon, Dec 10, 2018, 17:57 Ian Lepore > >> On Mon, 2018-12-10 at 14:15 -0800, John Baldwin wrote: >> > On 12/8/18 7:43 PM, Warner Losh wrote: >> > > >> > > >> > > >> > > On Sat, Dec 8, 2018, 8:36 PM Kevin Bowling > > > m wrote: >> > > >> > > On Sat, Dec 8, 2018 at 12:09 AM Mateusz Guzik > > > m > wrote: >> > > >> > > > >> > > > Fully satisfying solution would be that all architectures get >> > > 64-bit >> > > > ops, even if in the worst case they end up taking a lock. >> > > Then >> > > > subsystems would not have to ifdef on anything. However, >> > > there >> > > > was some opposition to this proposal and I don't think this >> > > is >> > > > important enough to push. >> > > >> > > Mateusz, >> > > >> > > Who is opposing this particular polyfill solution? Scott Long >> > > brought >> > > up a situation in driver development where this would be useful >> > > as >> > > well. The polyfills lower the cognitive load and #ifdef soup >> > > which >> > > are the right call here regardless of performance on toy ports. >> > > >> > > >> > > I don't recall seeing the opposition either. It would have to be a >> > > global lock for all 64bit atomics.... but I think it would only be >> > > 2 atomics on those architectures. >> > It would have to be a spin lock, so in the case of unrl you would be >> > trading >> > an operation on one of N regular mutexes for a single spin lock that >> > was >> > also contested by other things. This would be pretty crappy. For >> > drivers >> > that aren't actually used on platforms without 32-bit atomics we can >> > simply >> > not build them in sys/modules/Makefile or not put them in >> > GENERIC. For >> > something in the core kernel like unrl I think we will have to do >> > what >> > Mateusz has done here. >> > >> >> On a single-core system all you need to implement 64-bit atomics in the >> kernel is to disable interrupts around using normal load/store >> operations on the values. Do we have any platforms that are SMP but >> don't have hardware primitives for 64-bit atomics? >> >> -- Ian > > > There were some dual processor G4 machines. I have one. It doesn't have 64 bit atomics. > > - Justin