From owner-freebsd-arm@FreeBSD.ORG Tue Sep 9 17:02:05 2008 Return-Path: Delivered-To: freebsd-arm@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id 9BF3D1065675; Tue, 9 Sep 2008 17:02:05 +0000 (UTC) (envelope-from tinguely@casselton.net) Received: from casselton.net (casselton.net [63.165.140.2]) by mx1.freebsd.org (Postfix) with ESMTP id 597A08FC13; Tue, 9 Sep 2008 17:02:05 +0000 (UTC) (envelope-from tinguely@casselton.net) Received: from casselton.net (localhost [127.0.0.1]) by casselton.net (8.14.2/8.14.2) with ESMTP id m89H24Bt091764; Tue, 9 Sep 2008 12:02:04 -0500 (CDT) (envelope-from tinguely@casselton.net) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=casselton.net; s=ccnMail; t=1220979724; bh=1JfJjcdEdl1C2qQiCO4mw2+KxDAGub6FuCz52vT 7rEU=; h=Date:From:Message-Id:To:Subject:Cc:In-Reply-To; b=hRVA7GYC U+CevfCaXqBr0T6mV70mNo1C/pPaU5SiTNj7k5GslJiug9oe2de3VMIdru49VSEwS1J 4N/MyTpUeXEyanKmkE1e1sOVrkEeZzZR49P3L/sJlq2EuZm1PbLOYoSLLnCg7cwpCH5 awCdbZPrpjCGcPL+4KjjB2r/Kumso= Received: (from tinguely@localhost) by casselton.net (8.14.2/8.14.2/Submit) id m89H24Bs091763; Tue, 9 Sep 2008 12:02:04 -0500 (CDT) (envelope-from tinguely) Date: Tue, 9 Sep 2008 12:02:04 -0500 (CDT) From: Mark Tinguely Message-Id: <200809091702.m89H24Bs091763@casselton.net> To: jacques.fourie@gmail.com, tinguely@casselton.net In-Reply-To: Cc: freebsd-arm@freebsd.org, sam@freebsd.org Subject: Re: Routing benchmarks X-BeenThere: freebsd-arm@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: Porting FreeBSD to the StrongARM Processor List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 09 Sep 2008 17:02:05 -0000 (more trimmed thread text) I asked: > > which version of freebsd are you using - we changed some cache flushing > > routines between FreeBSD 7.x and current. Unless errors were introduced > > or removed, there should not be that large of a change. Jacques answered: > I'm using -current from about a week ago. I doubt FreeBSD 7.x will be faster, but it may be worth a try. Also a fourth item, If I remember correctly, the ARM DMA is done to RAM only. The cache had to be flushed before the read and write DMAs. Therefore, any access by the processor to the packet brought in by DMA (to do checksum, decrease the TTL, read header for packet for IP destination, etc), involves a cache miss. Also we need to flush the cache before another DMA can be performed - for example transmit the packet. I am hazy on remembering, but I think this cache non-involvement in DMA feature is still in the newer ARMv6/ARMv7 arch. These arch features can't be programmed around, but keeping the processor involvement in the packet as little are possible and profiling may tell us what we are doing inefficiently. --Mark Tinguely.