From owner-svn-src-head@freebsd.org Thu Sep 7 15:45:58 2017 Return-Path: Delivered-To: svn-src-head@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:1900:2254:206a::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id 61630E00658; Thu, 7 Sep 2017 15:45:58 +0000 (UTC) (envelope-from andrew@FreeBSD.org) Received: from repo.freebsd.org (repo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mx1.freebsd.org (Postfix) with ESMTPS id E6C346CEE5; Thu, 7 Sep 2017 15:45:57 +0000 (UTC) (envelope-from andrew@FreeBSD.org) Received: from repo.freebsd.org ([127.0.1.37]) by repo.freebsd.org (8.15.2/8.15.2) with ESMTP id v87FjulG011680; Thu, 7 Sep 2017 15:45:56 GMT (envelope-from andrew@FreeBSD.org) Received: (from andrew@localhost) by repo.freebsd.org (8.15.2/8.15.2/Submit) id v87FjuuO011678; Thu, 7 Sep 2017 15:45:56 GMT (envelope-from andrew@FreeBSD.org) Message-Id: <201709071545.v87FjuuO011678@repo.freebsd.org> X-Authentication-Warning: repo.freebsd.org: andrew set sender to andrew@FreeBSD.org using -f From: Andrew Turner Date: Thu, 7 Sep 2017 15:45:56 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r323271 - in head/sys/arm64: arm64 include X-SVN-Group: head X-SVN-Commit-Author: andrew X-SVN-Commit-Paths: in head/sys/arm64: arm64 include X-SVN-Commit-Revision: 323271 X-SVN-Commit-Repository: base MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-head@freebsd.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: SVN commit messages for the src tree for head/-current List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 07 Sep 2017 15:45:58 -0000 Author: andrew Date: Thu Sep 7 15:45:56 2017 New Revision: 323271 URL: https://svnweb.freebsd.org/changeset/base/323271 Log: Add the ARMv8.2 ID register additions and use them to decode the register values. As not all assemblers understand the new ID_AA64MMFR2_EL1 register add a macro to access it. This seems to be safe for older CPUs to read this new register, with them returning zero. Sponsored by: DARPA, AFRL Modified: head/sys/arm64/arm64/identcpu.c head/sys/arm64/include/armreg.h Modified: head/sys/arm64/arm64/identcpu.c ============================================================================== --- head/sys/arm64/arm64/identcpu.c Thu Sep 7 15:30:52 2017 (r323270) +++ head/sys/arm64/arm64/identcpu.c Thu Sep 7 15:45:56 2017 (r323271) @@ -80,6 +80,7 @@ struct cpu_desc { uint64_t id_aa64isar1; uint64_t id_aa64mmfr0; uint64_t id_aa64mmfr1; + uint64_t id_aa64mmfr2; uint64_t id_aa64pfr0; uint64_t id_aa64pfr1; }; @@ -94,6 +95,7 @@ static u_int cpu_print_regs; #define PRINT_ID_AA64_ISAR1 0x00000200 #define PRINT_ID_AA64_MMFR0 0x00001000 #define PRINT_ID_AA64_MMFR1 0x00002000 +#define PRINT_ID_AA64_MMFR2 0x00000100 #define PRINT_ID_AA64_PFR0 0x00010000 #define PRINT_ID_AA64_PFR1 0x00020000 @@ -305,14 +307,53 @@ print_cpu_features(u_int cpu) /* AArch64 Instruction Set Attribute Register 1 */ if (cpu == 0 || (cpu_print_regs & PRINT_ID_AA64_ISAR1) != 0) { - printf(" Instruction Set Attributes 1 = <%#lx>\n", - cpu_desc[cpu].id_aa64isar1); + printed = 0; + printf(" Instruction Set Attributes 1 = <"); + + switch (ID_AA64ISAR1_DPB(cpu_desc[cpu].id_aa64isar1)) { + case ID_AA64ISAR1_DPB_NONE: + break; + case ID_AA64ISAR1_DPB_IMPL: + printf("%sDC CVAP", SEP_STR); + break; + default: + printf("%sUnknown DC CVAP", SEP_STR); + break; + } + + if ((cpu_desc[cpu].id_aa64isar1 & ~ID_AA64ISAR1_MASK) != 0) + printf("%s%#lx", SEP_STR, + cpu_desc[cpu].id_aa64isar1 & ~ID_AA64ISAR1_MASK); + printf(">\n"); } /* AArch64 Processor Feature Register 0 */ if (cpu == 0 || (cpu_print_regs & PRINT_ID_AA64_PFR0) != 0) { printed = 0; printf(" Processor Features 0 = <"); + + switch (ID_AA64PFR0_SVE(cpu_desc[cpu].id_aa64pfr0)) { + case ID_AA64PFR0_SVE_NONE: + break; + case ID_AA64PFR0_SVE_IMPL: + printf("%sSVE", SEP_STR); + break; + default: + printf("%sUnknown SVE", SEP_STR); + break; + } + + switch (ID_AA64PFR0_RAS(cpu_desc[cpu].id_aa64pfr0)) { + case ID_AA64PFR0_RAS_NONE: + break; + case ID_AA64PFR0_RAS_V1: + printf("%sRASv1", SEP_STR); + break; + default: + printf("%sUnknown RAS", SEP_STR); + break; + } + switch (ID_AA64PFR0_GIC(cpu_desc[cpu].id_aa64pfr0)) { case ID_AA64PFR0_GIC_CPUIF_NONE: break; @@ -330,6 +371,9 @@ print_cpu_features(u_int cpu) case ID_AA64PFR0_ADV_SIMD_IMPL: printf("%sAdvSIMD", SEP_STR); break; + case ID_AA64PFR0_ADV_SIMD_HP: + printf("%sAdvSIMD+HP", SEP_STR); + break; default: printf("%sUnknown AdvSIMD", SEP_STR); break; @@ -341,6 +385,9 @@ print_cpu_features(u_int cpu) case ID_AA64PFR0_FP_IMPL: printf("%sFloat", SEP_STR); break; + case ID_AA64PFR0_FP_HP: + printf("%sFloat+HP", SEP_STR); + break; default: printf("%sUnknown Float", SEP_STR); break; @@ -514,6 +561,9 @@ print_cpu_features(u_int cpu) case ID_AA64MMFR0_PA_RANGE_256T: printf("%s256TB PA", SEP_STR); break; + case ID_AA64MMFR0_PA_RANGE_4P: + printf("%s4PB PA", SEP_STR); + break; default: printf("%sUnknown PA Range", SEP_STR); break; @@ -530,6 +580,28 @@ print_cpu_features(u_int cpu) printed = 0; printf(" Memory Model Features 1 = <"); + switch (ID_AA64MMFR1_XNX(cpu_desc[cpu].id_aa64mmfr1)) { + case ID_AA64MMFR1_XNX_NONE: + break; + case ID_AA64MMFR1_XNX_IMPL: + printf("%sEL2 XN", SEP_STR); + break; + default: + printf("%sUnknown XNX", SEP_STR); + break; + } + + switch (ID_AA64MMFR1_SPEC_SEI(cpu_desc[cpu].id_aa64mmfr1)) { + case ID_AA64MMFR1_SPEC_SEI_NONE: + break; + case ID_AA64MMFR1_SPEC_SEI_IMPL: + printf("%sSpecSEI", SEP_STR); + break; + default: + printf("%sUnknown SpecSEI", SEP_STR); + break; + } + switch (ID_AA64MMFR1_PAN(cpu_desc[cpu].id_aa64mmfr1)) { case ID_AA64MMFR1_PAN_NONE: break; @@ -555,9 +627,12 @@ print_cpu_features(u_int cpu) switch (ID_AA64MMFR1_HPDS(cpu_desc[cpu].id_aa64mmfr1)) { case ID_AA64MMFR1_HPDS_NONE: break; - case ID_AA64MMFR1_HPDS_IMPL: + case ID_AA64MMFR1_HPDS_HPD: printf("%sHPDS", SEP_STR); break; + case ID_AA64MMFR1_HPDS_TTPBHA: + printf("%sTTPBHA", SEP_STR); + break; default: printf("%sUnknown HPDS", SEP_STR); break; @@ -605,10 +680,88 @@ print_cpu_features(u_int cpu) printf(">\n"); } + /* AArch64 Memory Model Feature Register 2 */ + if (cpu == 0 || (cpu_print_regs & PRINT_ID_AA64_MMFR2) != 0) { + printed = 0; + printf(" Memory Model Features 2 = <"); + + switch (ID_AA64MMFR2_VA_RANGE(cpu_desc[cpu].id_aa64mmfr2)) { + case ID_AA64MMFR2_VA_RANGE_48: + printf("%s48b VA", SEP_STR); + break; + case ID_AA64MMFR2_VA_RANGE_52: + printf("%s52b VA", SEP_STR); + break; + default: + printf("%sUnknown VA Range", SEP_STR); + break; + } + + switch (ID_AA64MMFR2_IESB(cpu_desc[cpu].id_aa64mmfr2)) { + case ID_AA64MMFR2_IESB_NONE: + break; + case ID_AA64MMFR2_IESB_IMPL: + printf("%sIESB", SEP_STR); + break; + default: + printf("%sUnknown IESB", SEP_STR); + break; + } + + switch (ID_AA64MMFR2_LSM(cpu_desc[cpu].id_aa64mmfr2)) { + case ID_AA64MMFR2_LSM_NONE: + break; + case ID_AA64MMFR2_LSM_IMPL: + printf("%sLSM", SEP_STR); + break; + default: + printf("%sUnknown LSM", SEP_STR); + break; + } + + switch (ID_AA64MMFR2_UAO(cpu_desc[cpu].id_aa64mmfr2)) { + case ID_AA64MMFR2_UAO_NONE: + break; + case ID_AA64MMFR2_UAO_IMPL: + printf("%sUAO", SEP_STR); + break; + default: + printf("%sUnknown UAO", SEP_STR); + break; + } + + switch (ID_AA64MMFR2_CNP(cpu_desc[cpu].id_aa64mmfr2)) { + case ID_AA64MMFR2_CNP_NONE: + break; + case ID_AA64MMFR2_CNP_IMPL: + printf("%sCnP", SEP_STR); + break; + default: + printf("%sUnknown CnP", SEP_STR); + break; + } + + if ((cpu_desc[cpu].id_aa64mmfr2 & ~ID_AA64MMFR2_MASK) != 0) + printf("%s%#lx", SEP_STR, + cpu_desc[cpu].id_aa64mmfr2 & ~ID_AA64MMFR1_MASK); + printf(">\n"); + } + /* AArch64 Debug Feature Register 0 */ if (cpu == 0 || (cpu_print_regs & PRINT_ID_AA64_DFR0) != 0) { printed = 0; printf(" Debug Features 0 = <"); + switch(ID_AA64DFR0_PMS_VER(cpu_desc[cpu].id_aa64dfr0)) { + case ID_AA64DFR0_PMS_VER_NONE: + break; + case ID_AA64DFR0_PMS_VER_V1: + printf("%sSPE v1", SEP_STR); + break; + default: + printf("%sUnknown SPE", SEP_STR); + break; + } + printf("%s%lu CTX Breakpoints", SEP_STR, ID_AA64DFR0_CTX_CMPS(cpu_desc[cpu].id_aa64dfr0)); @@ -653,6 +806,9 @@ print_cpu_features(u_int cpu) case ID_AA64DFR0_DEBUG_VER_8_VHE: printf("%sDebug v8+VHE", SEP_STR); break; + case ID_AA64DFR0_DEBUG_VER_8_2: + printf("%sDebug v8.2", SEP_STR); + break; default: printf("%sUnknown Debug", SEP_STR); break; @@ -738,6 +894,7 @@ identify_cpu(void) cpu_desc[cpu].id_aa64isar1 = READ_SPECIALREG(ID_AA64ISAR1_EL1); cpu_desc[cpu].id_aa64mmfr0 = READ_SPECIALREG(ID_AA64MMFR0_EL1); cpu_desc[cpu].id_aa64mmfr1 = READ_SPECIALREG(ID_AA64MMFR1_EL1); + cpu_desc[cpu].id_aa64mmfr2 = READ_SPECIALREG(ID_AA64MMFR2_EL1); cpu_desc[cpu].id_aa64pfr0 = READ_SPECIALREG(ID_AA64PFR0_EL1); cpu_desc[cpu].id_aa64pfr1 = READ_SPECIALREG(ID_AA64PFR1_EL1); @@ -792,6 +949,8 @@ identify_cpu(void) cpu_print_regs |= PRINT_ID_AA64_MMFR0; if (cpu_desc[cpu].id_aa64mmfr1 != cpu_desc[0].id_aa64mmfr1) cpu_print_regs |= PRINT_ID_AA64_MMFR1; + if (cpu_desc[cpu].id_aa64mmfr2 != cpu_desc[0].id_aa64mmfr2) + cpu_print_regs |= PRINT_ID_AA64_MMFR2; if (cpu_desc[cpu].id_aa64pfr0 != cpu_desc[0].id_aa64pfr0) cpu_print_regs |= PRINT_ID_AA64_PFR0; Modified: head/sys/arm64/include/armreg.h ============================================================================== --- head/sys/arm64/include/armreg.h Thu Sep 7 15:30:52 2017 (r323270) +++ head/sys/arm64/include/armreg.h Thu Sep 7 15:45:56 2017 (r323271) @@ -167,12 +167,13 @@ #define ICC_SRE_EL2_EN (1U << 3) /* ID_AA64DFR0_EL1 */ -#define ID_AA64DFR0_MASK 0xf0f0ffff +#define ID_AA64DFR0_MASK 0x0000000ff0f0fffful #define ID_AA64DFR0_DEBUG_VER_SHIFT 0 #define ID_AA64DFR0_DEBUG_VER_MASK (0xf << ID_AA64DFR0_DEBUG_VER_SHIFT) #define ID_AA64DFR0_DEBUG_VER(x) ((x) & ID_AA64DFR0_DEBUG_VER_MASK) #define ID_AA64DFR0_DEBUG_VER_8 (0x6 << ID_AA64DFR0_DEBUG_VER_SHIFT) #define ID_AA64DFR0_DEBUG_VER_8_VHE (0x7 << ID_AA64DFR0_DEBUG_VER_SHIFT) +#define ID_AA64DFR0_DEBUG_VER_8_2 (0x8 << ID_AA64DFR0_DEBUG_VER_SHIFT) #define ID_AA64DFR0_TRACE_VER_SHIFT 4 #define ID_AA64DFR0_TRACE_VER_MASK (0xf << ID_AA64DFR0_TRACE_VER_SHIFT) #define ID_AA64DFR0_TRACE_VER(x) ((x) & ID_AA64DFR0_TRACE_VER_MASK) @@ -197,6 +198,11 @@ #define ID_AA64DFR0_CTX_CMPS_MASK (0xf << ID_AA64DFR0_CTX_CMPS_SHIFT) #define ID_AA64DFR0_CTX_CMPS(x) \ ((((x) >> ID_AA64DFR0_CTX_CMPS_SHIFT) & 0xf) + 1) +#define ID_AA64DFR0_PMS_VER_SHIFT 32 +#define ID_AA64DFR0_PMS_VER_MASK (0xful << ID_AA64DFR0_PMS_VER_SHIFT) +#define ID_AA64DFR0_PMS_VER(x) ((x) & ID_AA64DFR0_PMS_VER_MASK) +#define ID_AA64DFR0_PMS_VER_NONE (0x0ul << ID_AA64DFR0_PMS_VER_SHIFT) +#define ID_AA64DFR0_PMS_VER_V1 (0x1ul << ID_AA64DFR0_PMS_VER_SHIFT) /* ID_AA64ISAR0_EL1 */ #define ID_AA64ISAR0_MASK 0xf0fffff0 @@ -232,6 +238,14 @@ #define ID_AA64ISAR0_RDM_NONE (0x0 << ID_AA64ISAR0_RDM_SHIFT) #define ID_AA64ISAR0_RDM_IMPL (0x1 << ID_AA64ISAR0_RDM_SHIFT) +/* ID_AA64ISAR1_EL1 */ +#define ID_AA64ISAR1_MASK 0x0000000f +#define ID_AA64ISAR1_DPB_SHIFT 4 +#define ID_AA64ISAR1_DPB_MASK (0xf << ID_AA64ISAR1_DPB_SHIFT) +#define ID_AA64ISAR1_DPB(x) ((x) & ID_AA64ISAR1_DPB_MASK) +#define ID_AA64ISAR1_DPB_NONE (0x0 << ID_AA64ISAR1_DPB_SHIFT) +#define ID_AA64ISAR1_DPB_IMPL (0x1 << ID_AA64ISAR1_DPB_SHIFT) + /* ID_AA64MMFR0_EL1 */ #define ID_AA64MMFR0_MASK 0xffffffff #define ID_AA64MMFR0_PA_RANGE_SHIFT 0 @@ -243,6 +257,7 @@ #define ID_AA64MMFR0_PA_RANGE_4T (0x3 << ID_AA64MMFR0_PA_RANGE_SHIFT) #define ID_AA64MMFR0_PA_RANGE_16T (0x4 << ID_AA64MMFR0_PA_RANGE_SHIFT) #define ID_AA64MMFR0_PA_RANGE_256T (0x5 << ID_AA64MMFR0_PA_RANGE_SHIFT) +#define ID_AA64MMFR0_PA_RANGE_4P (0x6 << ID_AA64MMFR0_PA_RANGE_SHIFT) #define ID_AA64MMFR0_ASID_BITS_SHIFT 4 #define ID_AA64MMFR0_ASID_BITS_MASK (0xf << ID_AA64MMFR0_ASID_BITS_SHIFT) #define ID_AA64MMFR0_ASID_BITS(x) ((x) & ID_AA64MMFR0_ASID_BITS_MASK) @@ -280,7 +295,7 @@ #define ID_AA64MMFR0_TGRAN4_NONE (0xf << ID_AA64MMFR0_TGRAN4_SHIFT) /* ID_AA64MMFR1_EL1 */ -#define ID_AA64MMFR1_MASK 0x00ffffff +#define ID_AA64MMFR1_MASK 0xffffffff #define ID_AA64MMFR1_HAFDBS_SHIFT 0 #define ID_AA64MMFR1_HAFDBS_MASK (0xf << ID_AA64MMFR1_HAFDBS_SHIFT) #define ID_AA64MMFR1_HAFDBS(x) ((x) & ID_AA64MMFR1_HAFDBS_MASK) @@ -301,7 +316,8 @@ #define ID_AA64MMFR1_HPDS_MASK (0xf << ID_AA64MMFR1_HPDS_SHIFT) #define ID_AA64MMFR1_HPDS(x) ((x) & ID_AA64MMFR1_HPDS_MASK) #define ID_AA64MMFR1_HPDS_NONE (0x0 << ID_AA64MMFR1_HPDS_SHIFT) -#define ID_AA64MMFR1_HPDS_IMPL (0x1 << ID_AA64MMFR1_HPDS_SHIFT) +#define ID_AA64MMFR1_HPDS_HPD (0x1 << ID_AA64MMFR1_HPDS_SHIFT) +#define ID_AA64MMFR1_HPDS_TTPBHA (0x2 << ID_AA64MMFR1_HPDS_SHIFT) #define ID_AA64MMFR1_LO_SHIFT 16 #define ID_AA64MMFR1_LO_MASK (0xf << ID_AA64MMFR1_LO_SHIFT) #define ID_AA64MMFR1_LO(x) ((x) & ID_AA64MMFR1_LO_MASK) @@ -313,9 +329,48 @@ #define ID_AA64MMFR1_PAN_NONE (0x0 << ID_AA64MMFR1_PAN_SHIFT) #define ID_AA64MMFR1_PAN_IMPL (0x1 << ID_AA64MMFR1_PAN_SHIFT) #define ID_AA64MMFR1_PAN_ATS1E1 (0x2 << ID_AA64MMFR1_PAN_SHIFT) +#define ID_AA64MMFR1_SPEC_SEI_SHIFT 24 +#define ID_AA64MMFR1_SPEC_SEI_MASK (0xf << ID_AA64MMFR1_SPEC_SEI_SHIFT) +#define ID_AA64MMFR1_SPEC_SEI(x) ((x) & ID_AA64MMFR1_SPEC_SEI_MASK) +#define ID_AA64MMFR1_SPEC_SEI_NONE (0x0 << ID_AA64MMFR1_SPEC_SEI_SHIFT) +#define ID_AA64MMFR1_SPEC_SEI_IMPL (0x1 << ID_AA64MMFR1_SPEC_SEI_SHIFT) +#define ID_AA64MMFR1_XNX_SHIFT 28 +#define ID_AA64MMFR1_XNX_MASK (0xf << ID_AA64MMFR1_XNX_SHIFT) +#define ID_AA64MMFR1_XNX(x) ((x) & ID_AA64MMFR1_XNX_MASK) +#define ID_AA64MMFR1_XNX_NONE (0x0 << ID_AA64MMFR1_XNX_SHIFT) +#define ID_AA64MMFR1_XNX_IMPL (0x1 << ID_AA64MMFR1_XNX_SHIFT) +/* ID_AA64MMFR2_EL1 */ +#define ID_AA64MMFR2_EL1 S3_0_C0_C7_2 +#define ID_AA64MMFR2_MASK 0x000fffff +#define ID_AA64MMFR2_CNP_SHIFT 0 +#define ID_AA64MMFR2_CNP_MASK (0xf << ID_AA64MMFR2_CNP_SHIFT) +#define ID_AA64MMFR2_CNP(x) ((x) & ID_AA64MMFR2_CNP_MASK) +#define ID_AA64MMFR2_CNP_NONE (0x0 << ID_AA64MMFR2_CNP_SHIFT) +#define ID_AA64MMFR2_CNP_IMPL (0x1 << ID_AA64MMFR2_CNP_SHIFT) +#define ID_AA64MMFR2_UAO_SHIFT 4 +#define ID_AA64MMFR2_UAO_MASK (0xf << ID_AA64MMFR2_UAO_SHIFT) +#define ID_AA64MMFR2_UAO(x) ((x) & ID_AA64MMFR2_UAO_MASK) +#define ID_AA64MMFR2_UAO_NONE (0x0 << ID_AA64MMFR2_UAO_SHIFT) +#define ID_AA64MMFR2_UAO_IMPL (0x1 << ID_AA64MMFR2_UAO_SHIFT) +#define ID_AA64MMFR2_LSM_SHIFT 8 +#define ID_AA64MMFR2_LSM_MASK (0xf << ID_AA64MMFR2_LSM_SHIFT) +#define ID_AA64MMFR2_LSM(x) ((x) & ID_AA64MMFR2_LSM_MASK) +#define ID_AA64MMFR2_LSM_NONE (0x0 << ID_AA64MMFR2_LSM_SHIFT) +#define ID_AA64MMFR2_LSM_IMPL (0x1 << ID_AA64MMFR2_LSM_SHIFT) +#define ID_AA64MMFR2_IESB_SHIFT 12 +#define ID_AA64MMFR2_IESB_MASK (0xf << ID_AA64MMFR2_IESB_SHIFT) +#define ID_AA64MMFR2_IESB(x) ((x) & ID_AA64MMFR2_IESB_MASK) +#define ID_AA64MMFR2_IESB_NONE (0x0 << ID_AA64MMFR2_IESB_SHIFT) +#define ID_AA64MMFR2_IESB_IMPL (0x1 << ID_AA64MMFR2_IESB_SHIFT) +#define ID_AA64MMFR2_VA_RANGE_SHIFT 16 +#define ID_AA64MMFR2_VA_RANGE_MASK (0xf << ID_AA64MMFR2_VA_RANGE_SHIFT) +#define ID_AA64MMFR2_VA_RANGE(x) ((x) & ID_AA64MMFR2_VA_RANGE_MASK) +#define ID_AA64MMFR2_VA_RANGE_48 (0x0 << ID_AA64MMFR2_VA_RANGE_SHIFT) +#define ID_AA64MMFR2_VA_RANGE_52 (0x1 << ID_AA64MMFR2_VA_RANGE_SHIFT) + /* ID_AA64PFR0_EL1 */ -#define ID_AA64PFR0_MASK 0x0fffffff +#define ID_AA64PFR0_MASK 0x0000000ffffffffful #define ID_AA64PFR0_EL0_SHIFT 0 #define ID_AA64PFR0_EL0_MASK (0xf << ID_AA64PFR0_EL0_SHIFT) #define ID_AA64PFR0_EL0(x) ((x) & ID_AA64PFR0_EL0_MASK) @@ -342,11 +397,13 @@ #define ID_AA64PFR0_FP_MASK (0xf << ID_AA64PFR0_FP_SHIFT) #define ID_AA64PFR0_FP(x) ((x) & ID_AA64PFR0_FP_MASK) #define ID_AA64PFR0_FP_IMPL (0x0 << ID_AA64PFR0_FP_SHIFT) +#define ID_AA64PFR0_FP_HP (0x1 << ID_AA64PFR0_FP_SHIFT) #define ID_AA64PFR0_FP_NONE (0xf << ID_AA64PFR0_FP_SHIFT) #define ID_AA64PFR0_ADV_SIMD_SHIFT 20 #define ID_AA64PFR0_ADV_SIMD_MASK (0xf << ID_AA64PFR0_ADV_SIMD_SHIFT) #define ID_AA64PFR0_ADV_SIMD(x) ((x) & ID_AA64PFR0_ADV_SIMD_MASK) #define ID_AA64PFR0_ADV_SIMD_IMPL (0x0 << ID_AA64PFR0_ADV_SIMD_SHIFT) +#define ID_AA64PFR0_ADV_SIMD_HP (0x1 << ID_AA64PFR0_ADV_SIMD_SHIFT) #define ID_AA64PFR0_ADV_SIMD_NONE (0xf << ID_AA64PFR0_ADV_SIMD_SHIFT) #define ID_AA64PFR0_GIC_BITS 0x4 /* Number of bits in GIC field */ #define ID_AA64PFR0_GIC_SHIFT 24 @@ -354,6 +411,16 @@ #define ID_AA64PFR0_GIC(x) ((x) & ID_AA64PFR0_GIC_MASK) #define ID_AA64PFR0_GIC_CPUIF_NONE (0x0 << ID_AA64PFR0_GIC_SHIFT) #define ID_AA64PFR0_GIC_CPUIF_EN (0x1 << ID_AA64PFR0_GIC_SHIFT) +#define ID_AA64PFR0_RAS_SHIFT 28 +#define ID_AA64PFR0_RAS_MASK (0xf << ID_AA64PFR0_RAS_SHIFT) +#define ID_AA64PFR0_RAS(x) ((x) & ID_AA64PFR0_RAS_MASK) +#define ID_AA64PFR0_RAS_NONE (0x0 << ID_AA64PFR0_RAS_SHIFT) +#define ID_AA64PFR0_RAS_V1 (0x1 << ID_AA64PFR0_RAS_SHIFT) +#define ID_AA64PFR0_SVE_SHIFT 28 +#define ID_AA64PFR0_SVE_MASK (0xful << ID_AA64PFR0_SVE_SHIFT) +#define ID_AA64PFR0_SVE(x) ((x) & ID_AA64PFR0_SVE_MASK) +#define ID_AA64PFR0_SVE_NONE (0x0ul << ID_AA64PFR0_SVE_SHIFT) +#define ID_AA64PFR0_SVE_IMPL (0x1ul << ID_AA64PFR0_SVE_SHIFT) /* MAIR_EL1 - Memory Attribute Indirection Register */ #define MAIR_ATTR_MASK(idx) (0xff << ((n)* 8))