Date: Sun, 28 Mar 2010 03:00:19 +0000 (UTC) From: Juli Mallett <jmallett@FreeBSD.org> To: src-committers@freebsd.org, svn-src-user@freebsd.org Subject: svn commit: r205788 - in user/jmallett/octeon/sys/mips: include mips Message-ID: <201003280300.o2S30JX5079137@svn.freebsd.org>
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Author: jmallett Date: Sun Mar 28 03:00:18 2010 New Revision: 205788 URL: http://svn.freebsd.org/changeset/base/205788 Log: Consistency: o) Remove some extern functions for which there are drop-in replacements using inline functions. Modified: user/jmallett/octeon/sys/mips/include/cpu.h user/jmallett/octeon/sys/mips/mips/cpu.c user/jmallett/octeon/sys/mips/mips/machdep.c user/jmallett/octeon/sys/mips/mips/mp_machdep.c user/jmallett/octeon/sys/mips/mips/pmap.c user/jmallett/octeon/sys/mips/mips/support.S user/jmallett/octeon/sys/mips/mips/tlb.S Modified: user/jmallett/octeon/sys/mips/include/cpu.h ============================================================================== --- user/jmallett/octeon/sys/mips/include/cpu.h Sun Mar 28 02:48:39 2010 (r205787) +++ user/jmallett/octeon/sys/mips/include/cpu.h Sun Mar 28 03:00:18 2010 (r205788) @@ -456,11 +456,6 @@ struct user; u_int32_t mips_cp0_config1_read(void); int Mips_ConfigCache(void); -void Mips_SetWIRED(int); -void Mips_SetPID(int); -u_int Mips_GetCOUNT(void); -void Mips_SetCOMPARE(u_int); -u_int Mips_GetCOMPARE(void); void Mips_SyncCache(void); void Mips_SyncDCache(vm_offset_t, int); @@ -538,13 +533,9 @@ void setsoftintr1(void); void clearsoftintr1(void); -u_int32_t mips_cp0_status_read(void); -void mips_cp0_status_write(u_int32_t); - int disableintr(void); void restoreintr(int); int enableintr(void); -int Mips_TLBGetPID(void); void swi_vm(void *); void cpu_halt(void); Modified: user/jmallett/octeon/sys/mips/mips/cpu.c ============================================================================== --- user/jmallett/octeon/sys/mips/mips/cpu.c Sun Mar 28 02:48:39 2010 (r205787) +++ user/jmallett/octeon/sys/mips/mips/cpu.c Sun Mar 28 03:00:18 2010 (r205788) @@ -135,9 +135,9 @@ mips_cpu_init(void) platform_cpu_init(); mips_get_identity(&cpuinfo); num_tlbentries = cpuinfo.tlb_nentries; - Mips_SetWIRED(0); + mips_wr_wired(0); Mips_TLBFlush(num_tlbentries); - Mips_SetWIRED(VMWIRED_ENTRIES); + mips_wr_wired(VMWIRED_ENTRIES); mips_config_cache(&cpuinfo); mips_vector_init(); Modified: user/jmallett/octeon/sys/mips/mips/machdep.c ============================================================================== --- user/jmallett/octeon/sys/mips/mips/machdep.c Sun Mar 28 02:48:39 2010 (r205787) +++ user/jmallett/octeon/sys/mips/mips/machdep.c Sun Mar 28 03:00:18 2010 (r205788) @@ -377,7 +377,7 @@ mips_vector_init(void) enableintr(); /* Clear BEV in SR so we start handling our own exceptions */ - mips_cp0_status_write(mips_cp0_status_read() & ~SR_BOOT_EXC_VEC); + mips_wr_status(mips_rd_status() & ~SR_BOOT_EXC_VEC); } @@ -507,7 +507,7 @@ get_cyclecount(void) void cpu_idle(int busy) { - if (mips_cp0_status_read() & SR_INT_ENAB) + if (mips_rd_status() & SR_INT_ENAB) __asm __volatile ("wait"); else panic("ints disabled in idleproc!"); Modified: user/jmallett/octeon/sys/mips/mips/mp_machdep.c ============================================================================== --- user/jmallett/octeon/sys/mips/mips/mp_machdep.c Sun Mar 28 02:48:39 2010 (r205787) +++ user/jmallett/octeon/sys/mips/mips/mp_machdep.c Sun Mar 28 03:00:18 2010 (r205788) @@ -235,9 +235,9 @@ smp_init_secondary(u_int32_t cpuid) int ipi_int_mask, clock_int_mask; /* TLB */ - Mips_SetWIRED(0); + mips_wr_wired(0); Mips_TLBFlush(num_tlbentries); - Mips_SetWIRED(VMWIRED_ENTRIES); + mips_wr_wired(VMWIRED_ENTRIES); /* * We assume that the L1 cache on the APs is identical to the one @@ -246,7 +246,7 @@ smp_init_secondary(u_int32_t cpuid) mips_dcache_wbinv_all(); mips_icache_sync_all(); - Mips_SetPID(0); + mips_wr_entryhi(0 << VMTLB_PID_SHIFT); pcpu_init(PCPU_ADDR(cpuid), cpuid, sizeof(struct pcpu)); dpcpu_init(dpcpu, cpuid); Modified: user/jmallett/octeon/sys/mips/mips/pmap.c ============================================================================== --- user/jmallett/octeon/sys/mips/mips/pmap.c Sun Mar 28 02:48:39 2010 (r205787) +++ user/jmallett/octeon/sys/mips/mips/pmap.c Sun Mar 28 03:00:18 2010 (r205788) @@ -471,7 +471,7 @@ again: kernel_pmap->pm_asid[0].asid = PMAP_ASID_RESERVED; kernel_pmap->pm_asid[0].gen = 0; pmap_max_asid = VMNUM_PIDS; - Mips_SetPID(0); + mips_wr_entryhi(0 << VMTLB_PID_SHIFT); } /* @@ -596,7 +596,7 @@ pmap_TLB_invalidate_kernel(vm_offset_t v { u_int32_t pid; - pid = Mips_TLBGetPID(); + pid = mips_rd_entryhi() & VMTLB_PID; va = va | (pid << VMTLB_PID_SHIFT); Mips_TLBFlushAddr(va); } @@ -647,7 +647,7 @@ pmap_TLB_update_kernel(vm_offset_t va, p { u_int32_t pid; - pid = Mips_TLBGetPID(); + pid = mips_rd_entryhi() & VMTLB_PID; va = va | (pid << VMTLB_PID_SHIFT); Mips_TLBUpdate(va, pte); @@ -3112,7 +3112,7 @@ pmap_activate(struct thread *td) pmap_asid_alloc(pmap); if (td == curthread) { PCPU_SET(segbase, pmap->pm_segtab); - Mips_SetPID(pmap->pm_asid[PCPU_GET(cpuid)].asid); + mips_wr_entryhi(pmap->pm_asid[PCPU_GET(cpuid)].asid << VMTLB_PID_SHIFT); } PCPU_SET(curpmap, pmap); Modified: user/jmallett/octeon/sys/mips/mips/support.S ============================================================================== --- user/jmallett/octeon/sys/mips/mips/support.S Sun Mar 28 02:48:39 2010 (r205787) +++ user/jmallett/octeon/sys/mips/mips/support.S Sun Mar 28 03:00:18 2010 (r205788) @@ -656,83 +656,6 @@ LEAF(fswintrberr) li v0, -1 END(fswintrberr) -/*-------------------------------------------------------------------------- - * - * Mips_GetCOUNT -- - * - * Mips_GetCOUNT() - * - * Results: - * Returns the current COUNT reg. - * - * Side effects: - * None. - * - *-------------------------------------------------------------------------- - */ -LEAF(Mips_GetCOUNT) - mfc0 v0, COP_0_COUNT - nop #??? - nop #??? - j ra - nop -END(Mips_GetCOUNT) - -/*-------------------------------------------------------------------------- - * - * Mips_SetCOMPARE -- - * - * Mips_SetCOMPARE() - * - * Results: - * Sets a new value to the COMPARE register. - * - * Side effects: - * The COMPARE equal interrupt is acknowledged. - * - *-------------------------------------------------------------------------- - */ -LEAF(Mips_SetCOMPARE) - mtc0 a0, COP_0_COMPARE - j ra - nop -END(Mips_SetCOMPARE) - -LEAF(Mips_GetCOMPARE) - mfc0 v0, COP_0_COMPARE - j ra - nop -END(Mips_GetCOMPARE) - -/* - * u_int32_t mips_cp0_status_read(void) - * - * Return the current value of the CP0 Status register. - */ -LEAF(mips_cp0_status_read) - mfc0 v0, COP_0_STATUS_REG - j ra - nop -END(mips_cp0_status_read) - -/* - * void mips_cp0_status_write(u_int32_t) - * - * Set the value of the CP0 Status register. - * - * Note: This is almost certainly not the way you want to write a - * "permanent" value to to the CP0 Status register, since it gets - * saved in trap frames and restores. - */ -LEAF(mips_cp0_status_write) - mtc0 a0, COP_0_STATUS_REG - nop - nop - j ra - nop -END(mips_cp0_status_write) - - /* * memcpy(to, from, len) * {ov}bcopy(from, to, len) Modified: user/jmallett/octeon/sys/mips/mips/tlb.S ============================================================================== --- user/jmallett/octeon/sys/mips/mips/tlb.S Sun Mar 28 02:48:39 2010 (r205787) +++ user/jmallett/octeon/sys/mips/mips/tlb.S Sun Mar 28 03:00:18 2010 (r205788) @@ -134,68 +134,6 @@ END(Mips_TLBWriteIndexed) /*-------------------------------------------------------------------------- * - * Mips_SetPID(int pid); - * - * Write the given pid into the TLB pid reg. - * - * Results: - * None. - * - * Side effects: - * PID set in the entry hi register. - * - *-------------------------------------------------------------------------- - */ -LEAF(Mips_SetPID) - MTC0 a0, COP_0_TLB_HI # Write the hi reg value - nop # required for QED5230 - nop # required for QED5230 - j ra - nop -END(Mips_SetPID) - -/*-------------------------------------------------------------------------- - * - * Mips_SetWIRED(int wired); - * - * Write the given value into the TLB wired reg. - * - * Results: - * None. - * - * Side effects: - * WIRED set in the wired register. - * - *-------------------------------------------------------------------------- - */ -LEAF(Mips_SetWIRED) - mtc0 a0, COP_0_TLB_WIRED - j ra - nop -END(Mips_SetWIRED) - -/*-------------------------------------------------------------------------- - * - * Mips_GetWIRED(void); - * - * Get the value from the TLB wired reg. - * - * Results: - * Value of wired reg. - * - * Side effects: - * None. - * - *-------------------------------------------------------------------------- - */ -LEAF(Mips_GetWIRED) - mfc0 v0, COP_0_TLB_WIRED - j ra - nop -END(Mips_GetWIRED) - -/*-------------------------------------------------------------------------- - * * Mips_TLBFlush(tlbsize); * * Flush the "random" entries from the TLB. @@ -427,26 +365,6 @@ END(Mips_TLBRead) /*-------------------------------------------------------------------------- * - * Mips_TLBGetPID(void); - * - * Results: - * Returns the current TLB pid reg. - * - * Side effects: - * None. - * - *-------------------------------------------------------------------------- - */ -LEAF(Mips_TLBGetPID) - MFC0 v0, COP_0_TLB_HI # get PID - j ra - and v0, v0, VMTLB_PID # mask off PID -END(Mips_TLBGetPID) - - - -/*-------------------------------------------------------------------------- - * * void mips_TBIAP(int sizeofTLB); * * Invalidate TLB entries belong to per process user spaces while
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