Date: Mon, 19 Jun 2017 14:50:26 +0000 (UTC) From: Andriy Gapon <avg@FreeBSD.org> To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-stable@freebsd.org, svn-src-stable-10@freebsd.org Subject: svn commit: r320100 - in stable/10/sys: dev/hwpmc sys Message-ID: <201706191450.v5JEoQb2083206@repo.freebsd.org>
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Author: avg Date: Mon Jun 19 14:50:26 2017 New Revision: 320100 URL: https://svnweb.freebsd.org/changeset/base/320100 Log: MFC 281102: hwpmc: add initial Intel Broadwell support. Modified: stable/10/sys/dev/hwpmc/hwpmc_core.c stable/10/sys/dev/hwpmc/hwpmc_intel.c stable/10/sys/dev/hwpmc/pmc_events.h stable/10/sys/sys/pmc.h Directory Properties: stable/10/ (props changed) Modified: stable/10/sys/dev/hwpmc/hwpmc_core.c ============================================================================== --- stable/10/sys/dev/hwpmc/hwpmc_core.c Mon Jun 19 14:45:20 2017 (r320099) +++ stable/10/sys/dev/hwpmc/hwpmc_core.c Mon Jun 19 14:50:26 2017 (r320100) @@ -578,7 +578,8 @@ struct iap_event_descr { #define IAP_F_HW (1 << 10) /* CPU: Haswell */ #define IAP_F_CAS (1 << 11) /* CPU: Atom Silvermont */ #define IAP_F_HWX (1 << 12) /* CPU: Haswell Xeon */ -#define IAP_F_FM (1 << 13) /* Fixed mask */ +#define IAP_F_BW (1 << 13) /* CPU: Broadwell */ +#define IAP_F_FM (1 << 14) /* Fixed mask */ #define IAP_F_ALLCPUSCORE2 \ (IAP_F_CC | IAP_F_CC2 | IAP_F_CC2E | IAP_F_CA) @@ -2063,6 +2064,7 @@ iap_allocate_pmc(int cpu, int ri, struct pmc *pm, if (iap_event_corei7_ok_on_counter(ev, ri) == 0) return (EINVAL); break; + case PMC_CPU_INTEL_BROADWELL: case PMC_CPU_INTEL_SANDYBRIDGE: case PMC_CPU_INTEL_SANDYBRIDGE_XEON: case PMC_CPU_INTEL_IVYBRIDGE: @@ -2094,6 +2096,9 @@ iap_allocate_pmc(int cpu, int ri, struct pmc *pm, break; case PMC_CPU_INTEL_ATOM_SILVERMONT: cpuflag = IAP_F_CAS; + break; + case PMC_CPU_INTEL_BROADWELL: + cpuflag = IAP_F_BW; break; case PMC_CPU_INTEL_CORE: cpuflag = IAP_F_CC; Modified: stable/10/sys/dev/hwpmc/hwpmc_intel.c ============================================================================== --- stable/10/sys/dev/hwpmc/hwpmc_intel.c Mon Jun 19 14:45:20 2017 (r320099) +++ stable/10/sys/dev/hwpmc/hwpmc_intel.c Mon Jun 19 14:50:26 2017 (r320100) @@ -179,6 +179,10 @@ pmc_intel_initialize(void) cputype = PMC_CPU_INTEL_IVYBRIDGE_XEON; nclasses = 3; break; + case 0x3D: + cputype = PMC_CPU_INTEL_BROADWELL; + nclasses = 3; + break; case 0x3F: /* Per Intel document 325462-045US 09/2014. */ case 0x46: /* Per Intel document 325462-045US 09/2014. */ /* Should 46 be XEON. probably its own? */ @@ -227,6 +231,7 @@ pmc_intel_initialize(void) */ case PMC_CPU_INTEL_ATOM: case PMC_CPU_INTEL_ATOM_SILVERMONT: + case PMC_CPU_INTEL_BROADWELL: case PMC_CPU_INTEL_CORE: case PMC_CPU_INTEL_CORE2: case PMC_CPU_INTEL_CORE2EXTREME: @@ -295,6 +300,7 @@ pmc_intel_initialize(void) case PMC_CPU_INTEL_HASWELL: case PMC_CPU_INTEL_SANDYBRIDGE: case PMC_CPU_INTEL_WESTMERE: + case PMC_CPU_INTEL_BROADWELL: error = pmc_uncore_initialize(pmc_mdep, ncpus); break; default: @@ -319,6 +325,7 @@ pmc_intel_finalize(struct pmc_mdep *md) #if defined(__i386__) || defined(__amd64__) case PMC_CPU_INTEL_ATOM: case PMC_CPU_INTEL_ATOM_SILVERMONT: + case PMC_CPU_INTEL_BROADWELL: case PMC_CPU_INTEL_CORE: case PMC_CPU_INTEL_CORE2: case PMC_CPU_INTEL_CORE2EXTREME: @@ -360,6 +367,7 @@ pmc_intel_finalize(struct pmc_mdep *md) */ #if defined(__i386__) || defined(__amd64__) switch (md->pmd_cputype) { + case PMC_CPU_INTEL_BROADWELL: case PMC_CPU_INTEL_COREI7: case PMC_CPU_INTEL_HASWELL: case PMC_CPU_INTEL_SANDYBRIDGE: Modified: stable/10/sys/dev/hwpmc/pmc_events.h ============================================================================== --- stable/10/sys/dev/hwpmc/pmc_events.h Mon Jun 19 14:45:20 2017 (r320099) +++ stable/10/sys/dev/hwpmc/pmc_events.h Mon Jun 19 14:50:26 2017 (r320100) @@ -1540,6 +1540,11 @@ __PMC_EV_ALIAS("BACLEARS.RETURN", IAP_EVENT_E6H_0 __PMC_EV_ALIAS("BACLEARS.COND", IAP_EVENT_E6H_10H) \ __PMC_EV_ALIAS("MS_DECODED.MS_ENTRY", IAP_EVENT_E7H_01H) +/* + * Aliases for Broadwell PMC events. + */ +#define __PMC_EV_ALIAS_BROADWELL() \ +__PMC_EV_ALIAS_INTEL_ARCHITECTURAL() /* * Aliases for Core PMC events. @@ -4231,6 +4236,11 @@ __PMC_EV(UCP, EVENT_86H_01H) #define PMC_EV_UCP_FIRST PMC_EV_UCP_EVENT_00H_01H #define PMC_EV_UCP_LAST PMC_EV_UCP_EVENT_86H_01H + +/* + * Aliases for Broadwell uncore PMC events + */ +#define __PMC_EV_ALIAS_BROADWELLUC() #define __PMC_EV_ALIAS_COREI7UC() \ __PMC_EV_ALIAS("GQ_CYCLES_FULL.READ_TRACKER", UCP_EVENT_00H_01H) \ Modified: stable/10/sys/sys/pmc.h ============================================================================== --- stable/10/sys/sys/pmc.h Mon Jun 19 14:45:20 2017 (r320099) +++ stable/10/sys/sys/pmc.h Mon Jun 19 14:50:26 2017 (r320100) @@ -95,6 +95,7 @@ __PMC_CPU(INTEL_NEHALEM_EX, 0x93, "Intel Nehalem Xeon 7500") \ __PMC_CPU(INTEL_WESTMERE_EX, 0x94, "Intel Westmere Xeon E7") \ __PMC_CPU(INTEL_HASWELL_XEON, 0x95, "Intel Haswell Xeon E5 v3") \ + __PMC_CPU(INTEL_BROADWELL, 0x96, "Intel Broadwell") \ __PMC_CPU(INTEL_XSCALE, 0x100, "Intel XScale") \ __PMC_CPU(MIPS_24K, 0x200, "MIPS 24K") \ __PMC_CPU(MIPS_OCTEON, 0x201, "Cavium Octeon") \
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