From owner-svn-src-all@freebsd.org Wed Sep 19 23:45:19 2018 Return-Path: Delivered-To: svn-src-all@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id 9C68210AA8A1; Wed, 19 Sep 2018 23:45:19 +0000 (UTC) (envelope-from jhb@FreeBSD.org) Received: from mxrelay.nyi.freebsd.org (mxrelay.nyi.freebsd.org [IPv6:2610:1c1:1:606c::19:3]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client CN "mxrelay.nyi.freebsd.org", Issuer "Let's Encrypt Authority X3" (verified OK)) by mx1.freebsd.org (Postfix) with ESMTPS id 53A41703E3; Wed, 19 Sep 2018 23:45:19 +0000 (UTC) (envelope-from jhb@FreeBSD.org) Received: from repo.freebsd.org (repo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mxrelay.nyi.freebsd.org (Postfix) with ESMTPS id 4E85515ED6; Wed, 19 Sep 2018 23:45:19 +0000 (UTC) (envelope-from jhb@FreeBSD.org) Received: from repo.freebsd.org ([127.0.1.37]) by repo.freebsd.org (8.15.2/8.15.2) with ESMTP id w8JNjJQ1084202; Wed, 19 Sep 2018 23:45:19 GMT (envelope-from jhb@FreeBSD.org) Received: (from jhb@localhost) by repo.freebsd.org (8.15.2/8.15.2/Submit) id w8JNjIv3084198; Wed, 19 Sep 2018 23:45:18 GMT (envelope-from jhb@FreeBSD.org) Message-Id: <201809192345.w8JNjIv3084198@repo.freebsd.org> X-Authentication-Warning: repo.freebsd.org: jhb set sender to jhb@FreeBSD.org using -f From: John Baldwin Date: Wed, 19 Sep 2018 23:45:18 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r338814 - in head/sys/riscv: include riscv X-SVN-Group: head X-SVN-Commit-Author: jhb X-SVN-Commit-Paths: in head/sys/riscv: include riscv X-SVN-Commit-Revision: 338814 X-SVN-Commit-Repository: base MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-all@freebsd.org X-Mailman-Version: 2.1.27 Precedence: list List-Id: "SVN commit messages for the entire src tree \(except for " user" and " projects" \)" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 19 Sep 2018 23:45:19 -0000 Author: jhb Date: Wed Sep 19 23:45:18 2018 New Revision: 338814 URL: https://svnweb.freebsd.org/changeset/base/338814 Log: Various fixes for floating point on RISC-V. - Explicitly load an empty initial state into FP registers when taking the fault on the first FP instruction in a thread. Setting SSTATE.FS to INITIAL is just a marker to let context switch restore code know that it can load FP registers with zeroes instead of memory loads. It does not imply that the hardware will reset all registers to zero on first access. In addition, set the state to CLEAN instead of INITIAL after the first FP instruction. cpu_switch() doesn't do anything for INITIAL and only restores from the pcb if the state is CLEAN. We could perhaps change cpu_switch to call fpe_state_clear if the state was INITIAL and leave SSTATE.FS set to INITIAL instead of CLEAN after the first FP instruction. However, adding this complexity to cpu_switch() doesn't seem worth the supposed gain. - Only save the current FPU registers in fill_fpregs() if the request is made to save the current thread's registers. Previously if a debugger requested FP registers via ptrace() it was getting a copy of the debugger's FP registers rather than the debugee's. - Zero the entire FP register set structure returned for ptrace() if a thread hasn't used FP registers rather than leaking garbage in the fp_fcsr field. - If a debugger writes FP registers via ptrace(), always mark the pcb as having valid FP registers and set SSTATUS.FS_MASK to CLEAN so that the registers will be restored when the debugged thread resumes. - Be more explicit about clearing the SSTATUS.FS field before setting it to CLEAN on the first FP instruction trap. Submitted by: br, markj Approved by: re (rgrimes) Sponsored by: DARPA Differential Revision: https://reviews.freebsd.org/D17141 Modified: head/sys/riscv/include/fpe.h head/sys/riscv/riscv/machdep.c head/sys/riscv/riscv/swtch.S head/sys/riscv/riscv/trap.c Modified: head/sys/riscv/include/fpe.h ============================================================================== --- head/sys/riscv/include/fpe.h Wed Sep 19 22:53:52 2018 (r338813) +++ head/sys/riscv/include/fpe.h Wed Sep 19 23:45:18 2018 (r338814) @@ -34,5 +34,6 @@ #define _MACHINE_FPE_H_ void fpe_state_save(struct thread *td); +void fpe_state_clear(void); #endif /* !_MACHINE_FPE_H_ */ Modified: head/sys/riscv/riscv/machdep.c ============================================================================== --- head/sys/riscv/riscv/machdep.c Wed Sep 19 22:53:52 2018 (r338813) +++ head/sys/riscv/riscv/machdep.c Wed Sep 19 23:45:18 2018 (r338814) @@ -204,13 +204,14 @@ fill_fpregs(struct thread *td, struct fpreg *regs) * If we have just been running FPE instructions we will * need to save the state to memcpy it below. */ - fpe_state_save(td); + if (td == curthread) + fpe_state_save(td); memcpy(regs->fp_x, pcb->pcb_x, sizeof(regs->fp_x)); regs->fp_fcsr = pcb->pcb_fcsr; } else #endif - memset(regs->fp_x, 0, sizeof(regs->fp_x)); + memset(regs, 0, sizeof(*regs)); return (0); } @@ -219,12 +220,17 @@ int set_fpregs(struct thread *td, struct fpreg *regs) { #ifdef FPE + struct trapframe *frame; struct pcb *pcb; + frame = td->td_frame; pcb = td->td_pcb; memcpy(pcb->pcb_x, regs->fp_x, sizeof(regs->fp_x)); pcb->pcb_fcsr = regs->fp_fcsr; + pcb->pcb_fpflags |= PCB_FP_STARTED; + frame->tf_sstatus &= ~SSTATUS_FS_MASK; + frame->tf_sstatus |= SSTATUS_FS_CLEAN; #endif return (0); Modified: head/sys/riscv/riscv/swtch.S ============================================================================== --- head/sys/riscv/riscv/swtch.S Wed Sep 19 22:53:52 2018 (r338813) +++ head/sys/riscv/riscv/swtch.S Wed Sep 19 23:45:18 2018 (r338814) @@ -154,6 +154,59 @@ END(fpe_state_save) #endif /* FPE */ /* + * void + * fpe_state_clear(void) + */ +ENTRY(fpe_state_clear) + /* + * Enable FPE usage in supervisor mode, + * so we can access registers. + */ + li t0, SSTATUS_FS_INITIAL + csrs sstatus, t0 + + fscsr zero + fcvt.d.l f0, zero + fcvt.d.l f1, zero + fcvt.d.l f2, zero + fcvt.d.l f3, zero + fcvt.d.l f4, zero + fcvt.d.l f5, zero + fcvt.d.l f6, zero + fcvt.d.l f7, zero + fcvt.d.l f8, zero + fcvt.d.l f9, zero + fcvt.d.l f10, zero + fcvt.d.l f11, zero + fcvt.d.l f12, zero + fcvt.d.l f13, zero + fcvt.d.l f14, zero + fcvt.d.l f15, zero + fcvt.d.l f16, zero + fcvt.d.l f17, zero + fcvt.d.l f18, zero + fcvt.d.l f19, zero + fcvt.d.l f20, zero + fcvt.d.l f21, zero + fcvt.d.l f22, zero + fcvt.d.l f23, zero + fcvt.d.l f24, zero + fcvt.d.l f25, zero + fcvt.d.l f26, zero + fcvt.d.l f27, zero + fcvt.d.l f28, zero + fcvt.d.l f29, zero + fcvt.d.l f30, zero + fcvt.d.l f31, zero + + /* Disable FPE usage in supervisor mode. */ + li t0, SSTATUS_FS_MASK + csrc sstatus, t0 + + ret +END(fpe_state_clear) + +/* * void cpu_throw(struct thread *old, struct thread *new) */ ENTRY(cpu_throw) Modified: head/sys/riscv/riscv/trap.c ============================================================================== --- head/sys/riscv/riscv/trap.c Wed Sep 19 22:53:52 2018 (r338813) +++ head/sys/riscv/riscv/trap.c Wed Sep 19 23:45:18 2018 (r338814) @@ -57,6 +57,9 @@ __FBSDID("$FreeBSD$"); #include #include +#ifdef FPE +#include +#endif #include #include #include @@ -363,7 +366,9 @@ do_trap_user(struct trapframe *frame) * May be a FPE trap. Enable FPE usage * for this thread and try again. */ - frame->tf_sstatus |= SSTATUS_FS_INITIAL; + fpe_state_clear(); + frame->tf_sstatus &= ~SSTATUS_FS_MASK; + frame->tf_sstatus |= SSTATUS_FS_CLEAN; pcb->pcb_fpflags |= PCB_FP_STARTED; break; }