Date: Sat, 1 Oct 2011 16:50:55 +0800 From: Adrian Chadd <adrian@freebsd.org> To: "Jayachandran C." <jchandra@freebsd.org> Cc: svn-src-head@freebsd.org, svn-src-all@freebsd.org, src-committers@freebsd.org Subject: Re: svn commit: r225892 - head/sys/mips/mips Message-ID: <CAJ-Vmon32cVEVvC=3WJVmDkCUdyLWyec3sqU-ifzspVSPxedfg@mail.gmail.com> In-Reply-To: <CA%2B7sy7D6h5a08Q6yNfX6xSqwabDLzE5GLu5aV3fCMYQKn_4AoQ@mail.gmail.com> References: <201110010556.p915uQH6003016@svn.freebsd.org> <CA%2B7sy7BiRvTB79H9=y%2BS4jQ=%2BboW1bcDJn%2BBULMmJU9KLLVJ5A@mail.gmail.com> <CAJ-VmokAsDpjJLt%2BVJ2gDGX%2BiMAwZvL2TPaaAD_LRm-Yyquxig@mail.gmail.com> <CA%2B7sy7D6h5a08Q6yNfX6xSqwabDLzE5GLu5aV3fCMYQKn_4AoQ@mail.gmail.com>
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On 1 October 2011 15:21, Jayachandran C. <jchandra@freebsd.org> wrote: > I would like to understand this, reverting r216862 would take out the > critical_enter() and cpu_idleclock() which would keep the timer > interrupts coming is as usual, this should not affect the event timer. Because the fundamental problem still exists w/out preemption - netisr/taskqueue scheduling doesn't happen if it happens just before the wait call. I haven't verified that mav's timer stuff does the correct thing by configuring the clock timer to occur every 1000hz in this instance. I kinda hope so. If I flip on preemption, then this may be fixed, but flipping on preemption causes other issues on the single-core MIPS boards that I've used when doing high-throughput 11n NIC testing. I don't (yet) know why. In any case, I think it's worth writing per-platform/per-chip cpu_idle() functions and set it up at boot/probe time. I'll happy do it if you're happy to do the digging with XLR to ensure this is all handled accurately in that instance. I just don't have the deep MIPS clue needed to ensure this is all correct and noone really piped up to come up with a better solution. I really want to see this all work correctly. :) Adrian
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