Date: Sat, 1 Oct 2011 16:54:53 +0800 From: Adrian Chadd <adrian@freebsd.org> To: "Jayachandran C." <jchandra@freebsd.org> Cc: svn-src-head@freebsd.org, svn-src-all@freebsd.org, src-committers@freebsd.org Subject: Re: svn commit: r225892 - head/sys/mips/mips Message-ID: <CAJ-Vmomsq5PQzbCBmWob5juB9EqdcEoYV%2B9vwYjnJQYTo_%2B4kw@mail.gmail.com> In-Reply-To: <CAJ-Vmon32cVEVvC=3WJVmDkCUdyLWyec3sqU-ifzspVSPxedfg@mail.gmail.com> References: <201110010556.p915uQH6003016@svn.freebsd.org> <CA%2B7sy7BiRvTB79H9=y%2BS4jQ=%2BboW1bcDJn%2BBULMmJU9KLLVJ5A@mail.gmail.com> <CAJ-VmokAsDpjJLt%2BVJ2gDGX%2BiMAwZvL2TPaaAD_LRm-Yyquxig@mail.gmail.com> <CA%2B7sy7D6h5a08Q6yNfX6xSqwabDLzE5GLu5aV3fCMYQKn_4AoQ@mail.gmail.com> <CAJ-Vmon32cVEVvC=3WJVmDkCUdyLWyec3sqU-ifzspVSPxedfg@mail.gmail.com>
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.. and somehow linux mips code does do a variety of WAIT-y things; how is it they don't have the interrupt handling issues we do? Is it because they're doing preemption? If so, how do they accurately handle hz clock pulses when an interrupt may preempt things just before that wait instruction occurs? Adrian
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