Date: Sun, 4 Mar 2007 04:52:00 GMT From: Warner Losh <imp@FreeBSD.org> To: Perforce Change Reviews <perforce@freebsd.org> Subject: PERFORCE change 115294 for review Message-ID: <200703040452.l244q0Md097404@repoman.freebsd.org>
next in thread | raw e-mail | index | archive | help
http://perforce.freebsd.org/chv.cgi?CH=115294 Change 115294 by imp@imp_lighthouse on 2007/03/04 04:51:58 Initial, and mostly untested other than compile testing, support for the arm9e, arm10 and arm11 families of cores. I've likely missed stuff in this initial import, which I'll correct next. This support was taken wholesale from NetBSD. Minor, inconsequential changes made by me... Affected files ... .. //depot/projects/arm/src/sys/arm/arm/cpufunc.c#14 edit .. //depot/projects/arm/src/sys/arm/arm/identcpu.c#12 edit .. //depot/projects/arm/src/sys/arm/at91/files.at91#16 edit .. //depot/projects/arm/src/sys/arm/at91/std.at91#5 edit .. //depot/projects/arm/src/sys/arm/include/armreg.h#5 edit .. //depot/projects/arm/src/sys/arm/include/cpuconf.h#7 edit .. //depot/projects/arm/src/sys/arm/include/cpufunc.h#7 edit Differences ... ==== //depot/projects/arm/src/sys/arm/arm/cpufunc.c#14 (text+ko) ==== @@ -283,6 +283,64 @@ }; #endif /* CPU_ARM9 */ +#if defined(CPU_ARM9E) || defined(CPU_ARM10) +struct cpu_functions armv5_ec_cpufuncs = { + /* CPU functions */ + + cpufunc_id, /* id */ + cpufunc_nullop, /* cpwait */ + + /* MMU functions */ + + cpufunc_control, /* control */ + cpufunc_domains, /* Domain */ + armv5_ec_setttb, /* Setttb */ + cpufunc_faultstatus, /* Faultstatus */ + cpufunc_faultaddress, /* Faultaddress */ + + /* TLB functions */ + + armv4_tlb_flushID, /* tlb_flushID */ + arm10_tlb_flushID_SE, /* tlb_flushID_SE */ + armv4_tlb_flushI, /* tlb_flushI */ + arm10_tlb_flushI_SE, /* tlb_flushI_SE */ + armv4_tlb_flushD, /* tlb_flushD */ + armv4_tlb_flushD_SE, /* tlb_flushD_SE */ + + /* Cache operations */ + + armv5_ec_icache_sync_all, /* icache_sync_all */ + armv5_ec_icache_sync_range, /* icache_sync_range */ + + armv5_ec_dcache_wbinv_all, /* dcache_wbinv_all */ + armv5_ec_dcache_wbinv_range, /* dcache_wbinv_range */ +/*XXX*/ armv5_ec_dcache_wbinv_range, /* dcache_inv_range */ + armv5_ec_dcache_wb_range, /* dcache_wb_range */ + + armv5_ec_idcache_wbinv_all, /* idcache_wbinv_all */ + armv5_ec_idcache_wbinv_range, /* idcache_wbinv_range */ + + /* Other functions */ + + cpufunc_nullop, /* flush_prefetchbuf */ + armv4_drain_writebuf, /* drain_writebuf */ + cpufunc_nullop, /* flush_brnchtgt_C */ + (void *)cpufunc_nullop, /* flush_brnchtgt_E */ + + (void *)cpufunc_nullop, /* sleep */ + + /* Soft functions */ + + cpufunc_null_fixup, /* dataabt_fixup */ + cpufunc_null_fixup, /* prefetchabt_fixup */ + + arm10_context_switch, /* context_switch */ + + arm10_setup /* cpu setup */ + +}; +#endif /* CPU_ARM9E || CPU_ARM10 */ + #ifdef CPU_ARM10 struct cpu_functions arm10_cpufuncs = { /* CPU functions */ @@ -832,6 +890,16 @@ return 0; } #endif /* CPU_ARM9 */ +#if defined(CPU_ARM9E) || defined(CPU_ARM10) + if (cputype == CPU_ID_ARM926EJS || + cputype == CPU_ID_ARM1026EJS) { + cpufuncs = armv5_ec_cpufuncs; + cpu_reset_needs_v4_MMU_disable = 1; /* V4 or higher */ + get_cachetype_cp15(); + pmap_pte_init_generic(); + return 0; + } +#endif /* CPU_ARM9E || CPU_ARM10 */ #ifdef CPU_ARM10 if (/* cputype == CPU_ID_ARM1020T || */ cputype == CPU_ID_ARM1020E) { @@ -1394,10 +1462,12 @@ */ #if defined(CPU_ARM7TDMI) || defined(CPU_ARM8) || defined (CPU_ARM9) || \ + defined(CPU_ARM9E) || \ defined(CPU_SA110) || defined(CPU_SA1100) || defined(CPU_SA1110) || \ defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \ defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) || \ - defined(CPU_XSCALE_80219) || defined(CPU_XSCALE_81342) + defined(CPU_XSCALE_80219) || defined(CPU_XSCALE_81342) || \ + defined(CPU_ARM10) || defined(CPU_ARM11) #define IGN 0 #define OR 1 @@ -1639,7 +1709,7 @@ } #endif /* CPU_ARM9 */ -#ifdef CPU_ARM10 +#if defined(CPU_ARM9E) || defined(CPU_ARM10) struct cpu_option arm10_options[] = { { "cpu.cache", BIC, OR, (CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE) }, { "cpu.nocache", OR, BIC, (CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE) }, @@ -1682,7 +1752,7 @@ cpu_idcache_wbinv_all(); /* Now really make sure they are clean. */ - asm volatile ("mcr\tp15, 0, r0, c7, c7, 0" : : ); + __asm __volatile ("mcr\tp15, 0, r0, c7, c7, 0" : : ); /* Set the control register */ ctrl = cpuctrl; @@ -1691,7 +1761,57 @@ /* And again. */ cpu_idcache_wbinv_all(); } -#endif /* CPU_ARM10 */ +#endif /* CPU_ARM9E || CPU_ARM10 */ + +#ifdef CPU_ARM11 +struct cpu_option arm11_options[] = { + { "cpu.cache", BIC, OR, (CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE) }, + { "cpu.nocache", OR, BIC, (CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE) }, + { "arm11.cache", BIC, OR, (CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE) }, + { "arm11.icache", BIC, OR, CPU_CONTROL_IC_ENABLE }, + { "arm11.dcache", BIC, OR, CPU_CONTROL_DC_ENABLE }, + { NULL, IGN, IGN, 0 } +}; + +void +arm11_setup(args) + char *args; +{ + int cpuctrl, cpuctrlmask; + + cpuctrl = CPU_CONTROL_MMU_ENABLE | CPU_CONTROL_SYST_ENABLE + | CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE + /* | CPU_CONTROL_BPRD_ENABLE */; + cpuctrlmask = CPU_CONTROL_MMU_ENABLE | CPU_CONTROL_SYST_ENABLE + | CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE + | CPU_CONTROL_ROM_ENABLE | CPU_CONTROL_BPRD_ENABLE + | CPU_CONTROL_BEND_ENABLE | CPU_CONTROL_AFLT_ENABLE + | CPU_CONTROL_ROUNDROBIN | CPU_CONTROL_CPCLK; + +#ifndef ARM32_DISABLE_ALIGNMENT_FAULTS + cpuctrl |= CPU_CONTROL_AFLT_ENABLE; +#endif + + cpuctrl = parse_cpu_options(args, arm11_options, cpuctrl); + +#ifdef __ARMEB__ + cpuctrl |= CPU_CONTROL_BEND_ENABLE; +#endif + + /* Clear out the cache */ + cpu_idcache_wbinv_all(); + + /* Now really make sure they are clean. */ + __asm __volatile ("mcr\tp15, 0, r0, c7, c7, 0" : : ); + + /* Set the control register */ + curcpu()->ci_ctrl = cpuctrl; + cpu_control(0xffffffff, cpuctrl); + + /* And again. */ + cpu_idcache_wbinv_all(); +} +#endif /* CPU_ARM11 */ #ifdef CPU_SA110 struct cpu_option sa110_options[] = { ==== //depot/projects/arm/src/sys/arm/arm/identcpu.c#12 (text+ko) ==== @@ -70,9 +70,12 @@ CPU_CLASS_ARM8, CPU_CLASS_ARM9TDMI, CPU_CLASS_ARM9ES, + CPU_CLASS_ARM9EJS, CPU_CLASS_ARM10E, + CPU_CLASS_ARM10EJ, CPU_CLASS_SA1, - CPU_CLASS_XSCALE + CPU_CLASS_XSCALE, + CPU_CLASS_ARM11J }; static const char * const generic_steppings[16] = { @@ -119,6 +122,13 @@ "rev 12", "rev 13", "rev 14", "rev 15", }; +static const char * const i80219_steppings[16] = { + "step A-0", "rev 1", "rev 2", "rev 3", + "rev 4", "rev 5", "rev 6", "rev 7", + "rev 8", "rev 9", "rev 10", "rev 11", + "rev 12", "rev 13", "rev 14", "rev 15", +}; + static const char * const i80321_steppings[16] = { "step A-0", "step B-0", "rev 2", "rev 3", "rev 4", "rev 5", "rev 6", "rev 7", @@ -133,6 +143,7 @@ "rev 12", "rev 13", "rev 14", "rev 15", }; +/* Steppings for PXA2[15]0 */ static const char * const pxa2x0_steppings[16] = { "step A-0", "step A-1", "step B-0", "step B-1", "step B-2", "step C-0", "rev 6", "rev 7", @@ -140,6 +151,9 @@ "rev 12", "rev 13", "rev 14", "rev 15", }; +/* Steppings for PXA255/26x. + * rev 5: PXA26x B0, rev 6: PXA255 A0 + */ static const char * const pxa255_steppings[16] = { "rev 0", "rev 1", "rev 2", "step A-0", "rev 4", "step B-0", "step A-0", "rev 7", @@ -147,6 +161,14 @@ "rev 12", "rev 13", "rev 14", "rev 15", }; +/* Stepping for PXA27x */ +static const char * const pxa27x_steppings[16] = { + "step A-0", "step A-1", "step B-0", "step B-1", + "step C-0", "rev 5", "rev 6", "rev 7", + "rev 8", "rev 9", "rev 10", "rev 11", + "rev 12", "rev 13", "rev 14", "rev 15", +}; + static const char * const ixp425_steppings[16] = { "step 0 (A0)", "rev 1 (ARMv5TE)", "rev 2", "rev 3", "rev 4", "rev 5", "rev 6", "rev 7", @@ -205,6 +227,8 @@ generic_steppings }, { CPU_ID_ARM922T, CPU_CLASS_ARM9TDMI, "ARM922T", generic_steppings }, + { CPU_ID_ARM926EJS, CPU_CLASS_ARM9EJS, "ARM926EJ-S", + generic_steppings }, { CPU_ID_ARM940T, CPU_CLASS_ARM9TDMI, "ARM940T", generic_steppings }, { CPU_ID_ARM946ES, CPU_CLASS_ARM9ES, "ARM946E-S", @@ -220,6 +244,8 @@ generic_steppings }, { CPU_ID_ARM1022ES, CPU_CLASS_ARM10E, "ARM1022E-S", generic_steppings }, + { CPU_ID_ARM1026EJS, CPU_CLASS_ARM10EJ, "ARM1026EJ-S", + generic_steppings }, { CPU_ID_SA110, CPU_CLASS_SA1, "SA-110", sa110_steppings }, @@ -247,11 +273,12 @@ i81342_steppings }, { CPU_ID_80219_400, CPU_CLASS_XSCALE, "i80219 400MHz", - xscale_steppings }, - + i80219_steppings }, { CPU_ID_80219_600, CPU_CLASS_XSCALE, "i80219 600MHz", - xscale_steppings }, + i80219_steppings }, + { CPU_ID_PXA27X, CPU_CLASS_XSCALE, "PXA27x", + pxa27x_steppings }, { CPU_ID_PXA250A, CPU_CLASS_XSCALE, "PXA250", pxa2x0_steppings }, { CPU_ID_PXA210A, CPU_CLASS_XSCALE, "PXA210", @@ -272,6 +299,11 @@ { CPU_ID_IXP425_266, CPU_CLASS_XSCALE, "IXP425 266MHz", ixp425_steppings }, + { CPU_ID_ARM1136JS, CPU_CLASS_ARM11J, "ARM1136J-S", + generic_steppings }, + { CPU_ID_ARM1136JSR1, CPU_CLASS_ARM11J, "ARM1136J-S R1", + generic_steppings }, + { 0, CPU_CLASS_NONE, NULL, NULL } }; @@ -290,10 +322,13 @@ { "ARM7TDMI", "CPU_ARM7TDMI" }, /* CPU_CLASS_ARM7TDMI */ { "ARM8", "CPU_ARM8" }, /* CPU_CLASS_ARM8 */ { "ARM9TDMI", "CPU_ARM9TDMI" }, /* CPU_CLASS_ARM9TDMI */ - { "ARM9E-S", NULL }, /* CPU_CLASS_ARM9ES */ + { "ARM9E-S", "CPU_ARM9E" }, /* CPU_CLASS_ARM9ES */ + { "ARM9EJ-S", "CPU_ARM9E" }, /* CPU_CLASS_ARM9EJS */ { "ARM10E", "CPU_ARM10" }, /* CPU_CLASS_ARM10E */ + { "ARM10EJ", "CPU_ARM10" }, /* CPU_CLASS_ARM10EJ */ { "SA-1", "CPU_SA110" }, /* CPU_CLASS_SA1 */ { "XScale", "CPU_XSCALE_..." }, /* CPU_CLASS_XSCALE */ + { "ARM11J", "CPU_ARM11" }, /* CPU_CLASS_ARM11J */ }; /* @@ -317,7 +352,7 @@ "**unknown 11**", "**unknown 12**", "**unknown 13**", - "**unknown 14**", + "write-back-locking-C", "**unknown 15**", }; @@ -370,9 +405,13 @@ printf(" IDC enabled"); break; case CPU_CLASS_ARM9TDMI: + case CPU_CLASS_ARM9ES: + case CPU_CLASS_ARM9EJS: case CPU_CLASS_ARM10E: + case CPU_CLASS_ARM10EJ: case CPU_CLASS_SA1: case CPU_CLASS_XSCALE: + case CPU_CLASS_ARM11J: if ((ctrl & CPU_CONTROL_DC_ENABLE) == 0) printf(" DC disabled"); else ==== //depot/projects/arm/src/sys/arm/at91/files.at91#16 (text) ==== @@ -1,5 +1,7 @@ # $FreeBSD: src/sys/arm/at91/files.at91,v 1.7 2007/01/05 02:06:53 ticso Exp $ arm/arm/cpufunc_asm_arm9.S standard +arm/arm/cpufunc_asm_arm10.S standard +arm/arm/cpufunc_asm_armv5_ec.S standard arm/arm/irq_dispatch.S standard arm/at91/at91.c standard arm/at91/at91_bbiic.c optional at91_bbiic ==== //depot/projects/arm/src/sys/arm/at91/std.at91#5 (text) ==== @@ -2,6 +2,7 @@ files "../at91/files.at91" cpu CPU_ARM9 +cpu CPU_ARM9E makeoptions CONF_CFLAGS=-mcpu=arm9 makeoptions KERNPHYSADDR=0x20000000 makeoptions KERNVIRTADDR=0xc0000000 ==== //depot/projects/arm/src/sys/arm/include/armreg.h#5 (text+ko) ==== @@ -1,4 +1,4 @@ -/* $NetBSD: armreg.h,v 1.28 2003/10/31 16:30:15 scw Exp $ */ +/* $NetBSD: armreg.h,v 1.37 2007/01/06 00:50:54 christos Exp $ */ /*- * Copyright (c) 1998, 2001 Ben Harris @@ -40,6 +40,7 @@ #ifndef MACHINE_ARMREG_H #define MACHINE_ARMREG_H + #define INSN_SIZE 4 #define INSN_COND_MASK 0xf0000000 /* Condition mask */ #define PSR_MODE 0x0000001f /* mode mask */ @@ -65,6 +66,7 @@ #define CPU_ID_DEC 0x44000000 /* 'D' */ #define CPU_ID_INTEL 0x69000000 /* 'i' */ #define CPU_ID_TI 0x54000000 /* 'T' */ +#define CPU_ID_FARADAY 0x66000000 /* 'f' */ /* How to decide what format the CPUID is in. */ #define CPU_ID_ISOLD(x) (((x) & 0x0000f000) == 0x00000000) @@ -89,6 +91,8 @@ #define CPU_ID_ARCH_V5 0x00030000 #define CPU_ID_ARCH_V5T 0x00040000 #define CPU_ID_ARCH_V5TE 0x00050000 +#define CPU_ID_ARCH_V5TEJ 0x00060000 +#define CPU_ID_ARCH_V6 0x00070000 #define CPU_ID_VARIANT_MASK 0x00f00000 /* Next three nybbles are part number */ @@ -118,7 +122,7 @@ /* ARM7 CPUs -- [15:12] == 7 */ #define CPU_ID_ARM700 0x41007000 /* XXX This is a guess. */ #define CPU_ID_ARM710 0x41007100 -#define CPU_ID_ARM7500 0x41027100 /* XXX This is a guess. */ +#define CPU_ID_ARM7500 0x41027100 #define CPU_ID_ARM710A 0x41047100 /* inc ARM7100 */ #define CPU_ID_ARM7500FE 0x41077100 #define CPU_ID_ARM710T 0x41807100 @@ -131,15 +135,20 @@ #define CPU_ID_ARM920T 0x41129200 #define CPU_ID_ARM920T_ALT 0x41009200 #define CPU_ID_ARM922T 0x41029220 +#define CPU_ID_ARM926EJS 0x41069260 #define CPU_ID_ARM940T 0x41029400 /* XXX no MMU */ #define CPU_ID_ARM946ES 0x41049460 /* XXX no MMU */ #define CPU_ID_ARM966ES 0x41049660 /* XXX no MMU */ #define CPU_ID_ARM966ESR1 0x41059660 /* XXX no MMU */ #define CPU_ID_ARM1020E 0x4115a200 /* (AKA arm10 rev 1) */ #define CPU_ID_ARM1022ES 0x4105a220 +#define CPU_ID_ARM1026EJS 0x4106a260 +#define CPU_ID_ARM1136JS 0x4107b360 +#define CPU_ID_ARM1136JSR1 0x4117b360 #define CPU_ID_SA110 0x4401a100 #define CPU_ID_SA1100 0x4401a110 #define CPU_ID_TI925T 0x54029250 +#define CPU_ID_FA526 0x66015260 #define CPU_ID_SA1110 0x6901b110 #define CPU_ID_IXP1200 0x6901c120 #define CPU_ID_80200 0x69052000 @@ -151,6 +160,7 @@ #define CPU_ID_PXA210B 0x69052920 /* 3rd version Core */ #define CPU_ID_PXA250C 0x69052d00 /* 4th version Core */ #define CPU_ID_PXA210C 0x69052d20 /* 4th version Core */ +#define CPU_ID_PXA27X 0x69054110 #define CPU_ID_80321_400 0x69052420 #define CPU_ID_80321_600 0x69052430 #define CPU_ID_80321_400_B0 0x69052c20 @@ -300,4 +310,6 @@ #define INSN_COND_MASK 0xf0000000 /* Condition mask */ #define INSN_COND_AL 0xe0000000 /* Always condition */ +#define THUMB_INSN_SIZE 2 /* Some are 4 bytes. */ + #endif /* !MACHINE_ARMREG_H */ ==== //depot/projects/arm/src/sys/arm/include/cpuconf.h#7 (text+ko) ==== @@ -50,12 +50,22 @@ /* * Step 1: Count the number of CPU types configured into the kernel. */ -#define CPU_NTYPES 2 +#define CPU_NTYPES (defined(CPU_ARM7TDMI) + \ + defined(CPU_ARM8) + defined(CPU_ARM9) + \ + defined(CPU_ARM9E) + \ + defined(CPU_ARM10) + \ + defined(CPU_ARM11) + \ + defined(CPU_SA110) + defined(CPU_SA1100) + \ + defined(CPU_SA1110) + \ + defined(CPU_IXP12X0) + \ + defined(CPU_XSCALE_80200) + \ + defined(CPU_XSCALE_80321) + \ + defined(__CPU_XSCALE_PXA2XX) + \ + defined(CPU_XSCALE_IXP425)) /* * Step 2: Determine which ARM architecture versions are configured. */ - #if (defined(CPU_ARM7TDMI) || defined(CPU_ARM8) || defined(CPU_ARM9) || \ defined(CPU_SA110) || defined(CPU_SA1100) || defined(CPU_SA1110) || \ defined(CPU_IXP12X0) || defined(CPU_XSCALE_IXP425)) @@ -64,19 +74,34 @@ #define ARM_ARCH_4 0 #endif -#if (defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \ - defined(CPU_XSCALE_80219) || defined(CPU_XSCALE_81342) || \ - defined(CPU_XSCALE_PXA2X0)) || defined(CPU_ARM10) +#if (defined(CPU_ARM9E) || defined(CPU_ARM10) || \ + defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \ + defined(CPU_XSCALE_80219) || defined(CPU_XSCALE_81342) || \ + defined(CPU_XSCALE_PXA2X0)) #define ARM_ARCH_5 1 #else #define ARM_ARCH_5 0 #endif -#define ARM_NARCH (ARM_ARCH_4 + ARM_ARCH_5) +#if defined(CPU_ARM11) +#define ARM_ARCH_6 1 +#else +#define ARM_ARCH_6 0 +#endif + +#define ARM_NARCH (ARM_ARCH_4 + ARM_ARCH_5 + ARM_ARCH_6) #if ARM_NARCH == 0 && !defined(KLD_MODULE) && defined(_KERNEL) #error ARM_NARCH is 0 #endif +#if ARM_ARCH_5 || ARM_ARCH_6 +/* + * We could support Thumb code on v4T, but the lack of clean interworking + * makes that hard. + */ +#define THUMB_CODE +#endif + /* * Step 3: Define which MMU classes are configured: * @@ -99,7 +124,8 @@ #endif #if (defined(CPU_ARM6) || defined(CPU_ARM7) || defined(CPU_ARM7TDMI) || \ - defined(CPU_ARM8) || defined(CPU_ARM9) || defined(CPU_ARM10)) + defined(CPU_ARM8) || defined(CPU_ARM9) || defined(CPU_ARM9E) || \ + defined(CPU_ARM10) || defined(CPU_ARM11)) #define ARM_MMU_GENERIC 1 #else #define ARM_MMU_GENERIC 0 ==== //depot/projects/arm/src/sys/arm/include/cpufunc.h#7 (text+ko) ==== @@ -343,7 +343,7 @@ extern unsigned arm9_dcache_index_inc; #endif -#ifdef CPU_ARM10 +#if defined(CPU_ARM9E) || defined(CPU_ARM10) void arm10_setttb (u_int); void arm10_tlb_flushID_SE (u_int); @@ -370,8 +370,60 @@ extern unsigned arm10_dcache_index_inc; #endif -#if defined(CPU_ARM9) || defined(CPU_ARM10) || defined(CPU_SA110) || \ - defined(CPU_SA1100) || defined(CPU_SA1110) || \ +#ifdef CPU_ARM11 +void arm11_setttb (u_int); + +void arm11_tlb_flushID_SE (u_int); +void arm11_tlb_flushI_SE (u_int); + +void arm11_context_switch (void); + +void arm11_setup (char *string); +void arm11_tlb_flushID (void); +void arm11_tlb_flushI (void); +void arm11_tlb_flushD (void); +void arm11_tlb_flushD_SE (u_int va); + +void arm11_drain_writebuf (void); +#endif + +#if defined(CPU_ARM9E) || defined (CPU_ARM10) +void armv5_ec_setttb(u_int); + +void armv5_ec_icache_sync_all(void); +void armv5_ec_icache_sync_range(vm_offset_t, vm_size_t); + +void armv5_ec_dcache_wbinv_all(void); +void armv5_ec_dcache_wbinv_range(vm_offset_t, vm_size_t); +void armv5_ec_dcache_inv_range(vm_offset_t, vm_size_t); +void armv5_ec_dcache_wb_range(vm_offset_t, vm_size_t); + +void armv5_ec_idcache_wbinv_all(void); +void armv5_ec_idcache_wbinv_range(vm_offset_t, vm_size_t); +#endif + +#if defined (CPU_ARM10) || defined (CPU_ARM11) +void armv5_setttb(u_int); + +void armv5_icache_sync_all(void); +void armv5_icache_sync_range(vm_offset_t, vm_size_t); + +void armv5_dcache_wbinv_all(void); +void armv5_dcache_wbinv_range(vm_offset_t, vm_size_t); +void armv5_dcache_inv_range(vm_offset_t, vm_size_t); +void armv5_dcache_wb_range(vm_offset_t, vm_size_t); + +void armv5_idcache_wbinv_all(void); +void armv5_idcache_wbinv_range(vm_offset_t, vm_size_t); + +extern unsigned armv5_dcache_sets_max; +extern unsigned armv5_dcache_sets_inc; +extern unsigned armv5_dcache_index_max; +extern unsigned armv5_dcache_index_inc; +#endif + +#if defined(CPU_ARM9) || defined(CPU_ARM9E) || defined(CPU_ARM10) || \ + defined(CPU_SA110) || defined(CPU_SA1100) || defined(CPU_SA1110) || \ defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \ defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) || \ defined(CPU_XSCALE_80219) || defined(CPU_XSCALE_81342)
Want to link to this message? Use this URL: <https://mail-archive.FreeBSD.org/cgi/mid.cgi?200703040452.l244q0Md097404>