From owner-freebsd-arm@FreeBSD.ORG Fri Jun 1 20:57:03 2007 Return-Path: X-Original-To: freebsd-arm@freebsd.org Delivered-To: freebsd-arm@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [69.147.83.52]) by hub.freebsd.org (Postfix) with ESMTP id 4EBE016A468 for ; Fri, 1 Jun 2007 20:57:03 +0000 (UTC) (envelope-from nb@synthcom.com) Received: from synthcom.com (static-71-245-103-2.ptldor.fios.verizon.net [71.245.103.2]) by mx1.freebsd.org (Postfix) with ESMTP id 1595113C45E for ; Fri, 1 Jun 2007 20:57:02 +0000 (UTC) (envelope-from nb@synthcom.com) Received: from static-71-245-103-2.ptldor.fios.verizon.net (static-71-245-103-2.ptldor.fios.verizon.net [71.245.103.2]) by synthcom.com (8.13.8/8.13.8) with ESMTP id l51KJ7re055427 for ; Fri, 1 Jun 2007 13:19:07 -0700 (PDT) (envelope-from nb@synthcom.com) Date: Fri, 1 Jun 2007 13:19:07 -0700 (PDT) From: Neil Bradley cc: freebsd-arm@freebsd.org In-Reply-To: <62776.2001:6f8:101e:0:20e:cff:fe6d:6adb.1180696310.squirrel@webmail.alpha-tierchen.de> Message-ID: <20070601130758.M54915@synthcom.com> References: <62776.2001:6f8:101e:0:20e:cff:fe6d:6adb.1180696310.squirrel@webmail.alpha-tierchen.de> MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII; format=flowed X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-3.0 (synthcom.com [71.245.103.2]); Fri, 01 Jun 2007 13:19:07 -0700 (PDT) Subject: Re: Execution stops while enabling MMU X-BeenThere: freebsd-arm@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: Porting FreeBSD to the StrongARM Processor List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 01 Jun 2007 20:57:03 -0000 > I try to use FreeBSD with an AT91RM9200-based board similar to KB920X. I > use an existing boot loader (U-Boot running at 0x00000000) to copy the raw > binary kernel (not ELF) to the beginning of the SDRAM (0x20000000) and > execute it with the "go" command. But suddenly the execution stops while > enabling the MMU in src/sys/arm/arm/locore.S: > > /* Enable MMU */ > mrc p15, 0, r0, c1, c0, 0 > orr r0, r0, #CPU_CONTROL_MMU_ENABLE > mcr p15, 0, r0, c1, c0, 0 I'm a bit new to these parts, but I have done some MMU work with the XScale ARM (and other ARM CPUs), and enabling the MMU is a bit more complicated, especially dealing with ensuring the instruction pipelines aren't doing anything afterward when the MMU gets enabled. I didn't see the code that comes after this sequence, but here is my sequence for enabling the MMU, in hopes it will do some good. This assumes that virtual == physical for the sake of the code execution: mov r1, #1 mcr p15, 0, r0, c8, c7, 0 ; Flush I+D TLBs mcr p15, 0, r1, c7, c10, 4 ; Drain write and fill buffers ldr r2,=VirtualExecutionStart mrc p15, 0, r0, c1, c0, 0 orr r0, r0, #0x1000 ; Enable instruction cache orr r0, r0, #0x0800 ; Enable branch target buffer orr r0, r0, #0x0004 ; Enable data cache orr r0, r0, #0x0001 ; Enable MMU mcr p15, 0, r0, c1, c0, 0 mov pc, r2 nop nop nop VirtualExecutionStart .... As an aside, you might want to also enable the I and D cache (0x1004) along with the MMU enable, in addition to the branch target buffer (0x0800), as I have done above. The code sequence above has been validated on the Intel PXA270, Intel IXP4xx series, Atmel SAM9 ARM9 CPUs, and the Freescale MX31. Hope this helps! -->Neil ---------------------------------------------------------------------------- C. Neil Bradley - KE7IXP - The one eyed man in the land of the blind is not king. He's a prisoner.