Date: Thu, 19 Mar 2009 08:22:56 +0000 (UTC) From: Robert Noland <rnoland@FreeBSD.org> To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r190020 - head/sys/dev/drm Message-ID: <200903190822.n2J8MuBl053258@svn.freebsd.org>
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Author: rnoland Date: Thu Mar 19 08:22:56 2009 New Revision: 190020 URL: http://svn.freebsd.org/changeset/base/190020 Log: Pull in some suspend / resume changes from Intel's code Tested by: mav@ MFC after: 3 days Modified: head/sys/dev/drm/i915_drv.h head/sys/dev/drm/i915_reg.h head/sys/dev/drm/i915_suspend.c Modified: head/sys/dev/drm/i915_drv.h ============================================================================== --- head/sys/dev/drm/i915_drv.h Thu Mar 19 08:18:13 2009 (r190019) +++ head/sys/dev/drm/i915_drv.h Thu Mar 19 08:22:56 2009 (r190020) @@ -151,6 +151,8 @@ typedef struct drm_i915_private { u32 saveDSPACNTR; u32 saveDSPBCNTR; u32 saveDSPARB; + u32 saveRENDERSTANDBY; + u32 saveHWS; u32 savePIPEACONF; u32 savePIPEBCONF; u32 savePIPEASRC; @@ -232,8 +234,8 @@ typedef struct drm_i915_private { u8 saveAR_INDEX; u8 saveAR[21]; u8 saveDACMASK; - u8 saveDACDATA[256*3]; /* 256 3-byte colors */ u8 saveCR[37]; + struct { #ifdef __linux__ struct drm_mm gtt_space; @@ -651,7 +653,8 @@ extern int i915_wait_ring(struct drm_dev #define IS_G4X(dev) ((dev)->pci_device == 0x2E02 || \ (dev)->pci_device == 0x2E12 || \ - (dev)->pci_device == 0x2E22) + (dev)->pci_device == 0x2E22 || \ + IS_GM45(dev)) #define IS_G33(dev) ((dev)->pci_device == 0x29C2 || \ (dev)->pci_device == 0x29B2 || \ Modified: head/sys/dev/drm/i915_reg.h ============================================================================== --- head/sys/dev/drm/i915_reg.h Thu Mar 19 08:18:13 2009 (r190019) +++ head/sys/dev/drm/i915_reg.h Thu Mar 19 08:22:56 2009 (r190020) @@ -38,7 +38,7 @@ __FBSDID("$FreeBSD$"); #define INTEL_GMCH_MEM_64M 0x1 #define INTEL_GMCH_MEM_128M 0 -#define INTEL_855_GMCH_GMS_MASK (0x7 << 4) +#define INTEL_GMCH_GMS_MASK (0xf << 4) #define INTEL_855_GMCH_GMS_DISABLED (0x0 << 4) #define INTEL_855_GMCH_GMS_STOLEN_1M (0x1 << 4) #define INTEL_855_GMCH_GMS_STOLEN_4M (0x2 << 4) @@ -48,6 +48,12 @@ __FBSDID("$FreeBSD$"); #define INTEL_915G_GMCH_GMS_STOLEN_48M (0x6 << 4) #define INTEL_915G_GMCH_GMS_STOLEN_64M (0x7 << 4) +#define INTEL_GMCH_GMS_STOLEN_128M (0x8 << 4) +#define INTEL_GMCH_GMS_STOLEN_256M (0x9 << 4) +#define INTEL_GMCH_GMS_STOLEN_96M (0xa << 4) +#define INTEL_GMCH_GMS_STOLEN_160M (0xb << 4) +#define INTEL_GMCH_GMS_STOLEN_224M (0xc << 4) +#define INTEL_GMCH_GMS_STOLEN_352M (0xd << 4) /* PCI config space */ @@ -178,9 +184,27 @@ __FBSDID("$FreeBSD$"); #define DISPLAY_PLANE_B (1<<20) /* - * Instruction and interrupt control regs + * Fence registers */ +#define FENCE_REG_830_0 0x2000 +#define FENCE_REG_945_8 0x3000 +#define I830_FENCE_START_MASK 0x07f80000 +#define I830_FENCE_TILING_Y_SHIFT 12 +#define I830_FENCE_SIZE_BITS(size) ((ffs((size) >> 19) - 1) << 8) +#define I830_FENCE_PITCH_SHIFT 4 +#define I830_FENCE_REG_VALID (1<<0) + +#define I915_FENCE_START_MASK 0x0ff00000 +#define I915_FENCE_SIZE_BITS(size) ((ffs((size) >> 20) - 1) << 8) + +#define FENCE_REG_965_0 0x03000 +#define I965_FENCE_PITCH_SHIFT 2 +#define I965_FENCE_TILING_Y_SHIFT 1 +#define I965_FENCE_REG_VALID (1<<0) +/* + * Instruction and interrupt control regs + */ #define PRB0_TAIL 0x02030 #define PRB0_HEAD 0x02034 #define PRB0_START 0x02038 @@ -248,6 +272,7 @@ __FBSDID("$FreeBSD$"); #define CM0_RC_OP_FLUSH_DISABLE (1<<0) #define GFX_FLSH_CNTL 0x02170 /* 915+ only */ + /* * Framebuffer compression (915+ only) */ @@ -525,11 +550,17 @@ __FBSDID("$FreeBSD$"); #define DCC_ADDRESSING_MODE_DUAL_CHANNEL_INTERLEAVED (2 << 0) #define DCC_ADDRESSING_MODE_MASK (3 << 0) #define DCC_CHANNEL_XOR_DISABLE (1 << 10) +#define DCC_CHANNEL_XOR_BIT_17 (1 << 9) /** 965 MCH register controlling DRAM channel configuration */ #define C0DRB3 0x10206 #define C1DRB3 0x10606 +/** GM965 GM45 render standby register */ +#define MCHBAR_RENDER_STANDBY 0x111B8 + +#define PEG_BAND_GAP_DATA 0x14d68 + /* * Overlay regs */ @@ -593,6 +624,9 @@ __FBSDID("$FreeBSD$"); /* Hotplug control (945+ only) */ #define PORT_HOTPLUG_EN 0x61110 +#define HDMIB_HOTPLUG_INT_EN (1 << 29) +#define HDMIC_HOTPLUG_INT_EN (1 << 28) +#define HDMID_HOTPLUG_INT_EN (1 << 27) #define SDVOB_HOTPLUG_INT_EN (1 << 26) #define SDVOC_HOTPLUG_INT_EN (1 << 25) #define TV_HOTPLUG_INT_EN (1 << 18) @@ -600,6 +634,9 @@ __FBSDID("$FreeBSD$"); #define CRT_HOTPLUG_FORCE_DETECT (1 << 3) #define PORT_HOTPLUG_STAT 0x61114 +#define HDMIB_HOTPLUG_INT_STATUS (1 << 29) +#define HDMIC_HOTPLUG_INT_STATUS (1 << 28) +#define HDMID_HOTPLUG_INT_STATUS (1 << 27) #define CRT_HOTPLUG_INT_STATUS (1 << 11) #define TV_HOTPLUG_INT_STATUS (1 << 10) #define CRT_HOTPLUG_MONITOR_MASK (3 << 8) @@ -629,7 +666,16 @@ __FBSDID("$FreeBSD$"); #define SDVO_PHASE_SELECT_DEFAULT (6 << 19) #define SDVO_CLOCK_OUTPUT_INVERT (1 << 18) #define SDVOC_GANG_MODE (1 << 16) +#define SDVO_ENCODING_SDVO (0x0 << 10) +#define SDVO_ENCODING_HDMI (0x2 << 10) +/** Requird for HDMI operation */ +#define SDVO_NULL_PACKETS_DURING_VSYNC (1 << 9) #define SDVO_BORDER_ENABLE (1 << 7) +#define SDVO_AUDIO_ENABLE (1 << 6) +/** New with 965, default is to be set */ +#define SDVO_VSYNC_ACTIVE_HIGH (1 << 4) +/** New with 965, default is to be set */ +#define SDVO_HSYNC_ACTIVE_HIGH (1 << 3) #define SDVOB_PCIE_CONCURRENCY (1 << 3) #define SDVO_DETECTED (1 << 2) /* Bits to be preserved when writing */ @@ -1403,6 +1449,7 @@ __FBSDID("$FreeBSD$"); #define PIPEB_FRMCOUNT_GM45 0x71040 #define PIPEB_FLIPCOUNT_GM45 0x71044 + /* Display B control */ #define DSPBCNTR 0x71180 #define DISPPLANE_ALPHA_TRANS_ENABLE (1<<15) Modified: head/sys/dev/drm/i915_suspend.c ============================================================================== --- head/sys/dev/drm/i915_suspend.c Thu Mar 19 08:18:13 2009 (r190019) +++ head/sys/dev/drm/i915_suspend.c Thu Mar 19 08:22:56 2009 (r190020) @@ -125,11 +125,6 @@ static void i915_save_vga(struct drm_dev /* VGA color palette registers */ dev_priv->saveDACMASK = I915_READ8(VGA_DACMASK); - /* DACCRX automatically increments during read */ - I915_WRITE8(VGA_DACRX, 0); - /* Read 3 bytes of color data from each index */ - for (i = 0; i < 256 * 3; i++) - dev_priv->saveDACDATA[i] = I915_READ8(VGA_DACDATA); /* MSR bits */ dev_priv->saveMSR = I915_READ8(VGA_MSR_READ); @@ -231,12 +226,6 @@ static void i915_restore_vga(struct drm_ /* VGA color palette registers */ I915_WRITE8(VGA_DACMASK, dev_priv->saveDACMASK); - /* DACCRX automatically increments during read */ - I915_WRITE8(VGA_DACWX, 0); - /* Read 3 bytes of color data from each index */ - for (i = 0; i < 256 * 3; i++) - I915_WRITE8(VGA_DACDATA, dev_priv->saveDACDATA[i]); - } int i915_save_state(struct drm_device *dev) @@ -250,6 +239,13 @@ int i915_save_state(struct drm_device *d pci_read_config_byte(dev->pdev, LBB, &dev_priv->saveLBB); #endif + /* Render Standby */ + if (IS_I965G(dev) && IS_MOBILE(dev)) + dev_priv->saveRENDERSTANDBY = I915_READ(MCHBAR_RENDER_STANDBY); + + /* Hardware status page */ + dev_priv->saveHWS = I915_READ(HWS_PGA); + /* Display arbitration control */ dev_priv->saveDSPARB = I915_READ(DSPARB); @@ -379,6 +375,14 @@ int i915_restore_state(struct drm_device pci_write_config_byte(dev->pdev, LBB, dev_priv->saveLBB); #endif + /* Render Standby */ + if (IS_I965G(dev) && IS_MOBILE(dev)) + I915_WRITE(MCHBAR_RENDER_STANDBY, dev_priv->saveRENDERSTANDBY); + + /* Hardware status page */ + I915_WRITE(HWS_PGA, dev_priv->saveHWS); + + /* Display arbitration */ I915_WRITE(DSPARB, dev_priv->saveDSPARB); /* Pipe & plane A info */
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