From owner-svn-src-all@freebsd.org Tue Oct 25 13:46:01 2016 Return-Path: Delivered-To: svn-src-all@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:1900:2254:206a::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id 14393C216DD; Tue, 25 Oct 2016 13:46:01 +0000 (UTC) (envelope-from andrew@FreeBSD.org) Received: from repo.freebsd.org (repo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mx1.freebsd.org (Postfix) with ESMTPS id DECD7834; Tue, 25 Oct 2016 13:46:00 +0000 (UTC) (envelope-from andrew@FreeBSD.org) Received: from repo.freebsd.org ([127.0.1.37]) by repo.freebsd.org (8.15.2/8.15.2) with ESMTP id u9PDjx2n093617; Tue, 25 Oct 2016 13:45:59 GMT (envelope-from andrew@FreeBSD.org) Received: (from andrew@localhost) by repo.freebsd.org (8.15.2/8.15.2/Submit) id u9PDjx7g093616; Tue, 25 Oct 2016 13:45:59 GMT (envelope-from andrew@FreeBSD.org) Message-Id: <201610251345.u9PDjx7g093616@repo.freebsd.org> X-Authentication-Warning: repo.freebsd.org: andrew set sender to andrew@FreeBSD.org using -f From: Andrew Turner Date: Tue, 25 Oct 2016 13:45:59 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r307907 - head/sys/arm/include X-SVN-Group: head MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-all@freebsd.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: "SVN commit messages for the entire src tree \(except for " user" and " projects" \)" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 25 Oct 2016 13:46:01 -0000 Author: andrew Date: Tue Oct 25 13:45:59 2016 New Revision: 307907 URL: https://svnweb.freebsd.org/changeset/base/307907 Log: Update the armv6 tlb handling functions to detect if it is running on hardware that supports the mp extensions. If so it should use the broadcast tlb invalidate instructions as other CPUs or devices may need to know about the invalidation. To simplify the code have the compiler optimise out the else case when not builing for Cortex-A8. Sponsored by: ABT Systems Ltd Differential Revision: https://reviews.freebsd.org/D8092 Modified: head/sys/arm/include/cpu-v6.h Modified: head/sys/arm/include/cpu-v6.h ============================================================================== --- head/sys/arm/include/cpu-v6.h Tue Oct 25 12:58:36 2016 (r307906) +++ head/sys/arm/include/cpu-v6.h Tue Oct 25 13:45:59 2016 (r307907) @@ -347,12 +347,21 @@ tlb_flush_range_local(vm_offset_t va, vm /* Broadcasting operations. */ #if __ARM_ARCH >= 7 && defined SMP +#if defined(CPU_CORTEXA8) +#define ARM_HAVE_MP_EXTENSIONS (cpuinfo.mp_ext != 0) +#else +#define ARM_HAVE_MP_EXTENSIONS 1 +#endif + static __inline void tlb_flush_all(void) { dsb(); - _CP15_TLBIALLIS(); + if (ARM_HAVE_MP_EXTENSIONS) + _CP15_TLBIALLIS(); + else + _CP15_TLBIALL(); dsb(); } @@ -361,7 +370,10 @@ tlb_flush_all_ng(void) { dsb(); - _CP15_TLBIASIDIS(CPU_ASID_KERNEL); + if (ARM_HAVE_MP_EXTENSIONS) + _CP15_TLBIASIDIS(CPU_ASID_KERNEL); + else + _CP15_TLBIASID(CPU_ASID_KERNEL); dsb(); } @@ -372,7 +384,10 @@ tlb_flush(vm_offset_t va) KASSERT((va & PAGE_MASK) == 0, ("%s: va %#x not aligned", __func__, va)); dsb(); - _CP15_TLBIMVAAIS(va); + if (ARM_HAVE_MP_EXTENSIONS) + _CP15_TLBIMVAAIS(va); + else + _CP15_TLBIMVA(va | CPU_ASID_KERNEL); dsb(); } @@ -386,8 +401,13 @@ tlb_flush_range(vm_offset_t va, vm_size size)); dsb(); - for (; va < eva; va += PAGE_SIZE) - _CP15_TLBIMVAAIS(va); + if (ARM_HAVE_MP_EXTENSIONS) { + for (; va < eva; va += PAGE_SIZE) + _CP15_TLBIMVAAIS(va); + } else { + for (; va < eva; va += PAGE_SIZE) + _CP15_TLBIMVA(va | CPU_ASID_KERNEL); + } dsb(); } #else /* SMP */ @@ -411,19 +431,23 @@ icache_sync(vm_offset_t va, vm_size_t si dsb(); va &= ~cpuinfo.dcache_line_mask; - for ( ; va < eva; va += cpuinfo.dcache_line_size) { #if __ARM_ARCH >= 7 && defined SMP - _CP15_DCCMVAU(va); -#else - _CP15_DCCMVAC(va); + if (ARM_HAVE_MP_EXTENSIONS) { + for ( ; va < eva; va += cpuinfo.dcache_line_size) + _CP15_DCCMVAU(va); + } else #endif + { + for ( ; va < eva; va += cpuinfo.dcache_line_size) + _CP15_DCCMVAC(va); } dsb(); #if __ARM_ARCH >= 7 && defined SMP - _CP15_ICIALLUIS(); -#else - _CP15_ICIALLU(); + if (ARM_HAVE_MP_EXTENSIONS) + _CP15_ICIALLUIS(); + else #endif + _CP15_ICIALLU(); dsb(); isb(); } @@ -433,10 +457,11 @@ static __inline void icache_inv_all(void) { #if __ARM_ARCH >= 7 && defined SMP - _CP15_ICIALLUIS(); -#else - _CP15_ICIALLU(); + if (ARM_HAVE_MP_EXTENSIONS) + _CP15_ICIALLUIS(); + else #endif + _CP15_ICIALLU(); dsb(); isb(); } @@ -446,10 +471,11 @@ static __inline void bpb_inv_all(void) { #if __ARM_ARCH >= 7 && defined SMP - _CP15_BPIALLIS(); -#else - _CP15_BPIALL(); + if (ARM_HAVE_MP_EXTENSIONS) + _CP15_BPIALLIS(); + else #endif + _CP15_BPIALL(); dsb(); isb(); } @@ -462,12 +488,15 @@ dcache_wb_pou(vm_offset_t va, vm_size_t dsb(); va &= ~cpuinfo.dcache_line_mask; - for ( ; va < eva; va += cpuinfo.dcache_line_size) { #if __ARM_ARCH >= 7 && defined SMP - _CP15_DCCMVAU(va); -#else - _CP15_DCCMVAC(va); + if (ARM_HAVE_MP_EXTENSIONS) { + for ( ; va < eva; va += cpuinfo.dcache_line_size) + _CP15_DCCMVAU(va); + } else #endif + { + for ( ; va < eva; va += cpuinfo.dcache_line_size) + _CP15_DCCMVAC(va); } dsb(); }