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Date:      Tue, 4 Mar 2008 12:18:10 GMT
From:      "Randall R. Stewart" <rrs@FreeBSD.org>
To:        Perforce Change Reviews <perforce@freebsd.org>
Subject:   PERFORCE change 136809 for review
Message-ID:  <200803041218.m24CIAU9091832@repoman.freebsd.org>

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http://perforce.freebsd.org/chv.cgi?CH=136809

Change 136809 by rrs@rrs-mips2-jnpr on 2008/03/04 12:17:53

	Carefully disable interrupts, not just blindly stuff
	       0 into the SR, instead, mask in the old value with
	       INT_IE and INT_EXL off.

Affected files ...

.. //depot/projects/mips2-jnpr/src/sys/mips/mips/exception.S#20 edit

Differences ...

==== //depot/projects/mips2-jnpr/src/sys/mips/mips/exception.S#20 (text+ko) ====

@@ -263,17 +263,22 @@
 #ifdef TARGET_OCTEON
 #define CLEAR_STATUS \
 	mfc0    a0, COP_0_STATUS_REG    ;\
-        li      a2, ~(SR_INT_ENAB | SR_EXL | SR_KSU_MASK) ;\
-        and     a0, a0, a2              ;\
-	or      a0, a0, (MIPS_SR_KX | MIPS_SR_SX | MIPS_SR_UX) ; \
+	li      a2, (MIPS_SR_KX | MIPS_SR_SX | MIPS_SR_UX) ; \
+	or      a0, a0, a2	        ; \
+	li      a2, ~(MIPS_SR_INT_IE|MIPS_SR_EXL)   ; \
+	and     a0, a0, a2              ; \
         mtc0    a0, COP_0_STATUS_REG    
 #else
 #define CLEAR_STATUS \
-	mtc0	zero, COP_0_STATUS_REG
+	mfc0    a0, COP_0_STATUS_REG    ;\
+	li      a2, ~(MIPS_SR_INT_IE|MIPS_SR_EXL)   ; \
+	and     a0, a0, a2              ; \
+	mtc0	a0, COP_0_STATUS_REG
 #endif
 
 #define	SAVE_CPU \
 	SAVE_REG(AT, AST, sp)		;\
+	.set	at		        ; \
 	SAVE_REG(v0, V0, sp)		;\
 	SAVE_REG(v1, V1, sp)		;\
 	SAVE_REG(a0, A0, sp)		;\
@@ -331,6 +336,7 @@
 	mtlo	t0			;\
 	mthi	t1			;\
 	_MTC0	v0, COP_0_EXC_PC	;\
+	.set noat		        ; \
 	RESTORE_REG(AT, AST, sp)	;\
 	RESTORE_REG(v0, V0, sp)		;\
 	RESTORE_REG(v1, V1, sp)		;\
@@ -545,8 +551,7 @@
 #ifdef TARGET_OCTEON
 	and k0, k0, ~(MIPS_SR_KX | MIPS_SR_SX | MIPS_SR_UX)
 #endif
-	or  k0, k0, MIPS_SR_INT_IE
-
+	or  k0, k0, (MIPS_SR_INT_IE)
 	.set noat
 	RESTORE_U_PCB_REG(AT, AST, k1)
 
@@ -587,6 +592,7 @@
  * Save the relevant kernel registers onto the stack.
  */
 	SAVE_CPU
+        
 /*
  * Call the interrupt handler.
  */
@@ -603,7 +609,6 @@
 	RESTORE_CPU
 	sync
 	eret
-
 	.set	at
 END(MipsKernIntr)
 
@@ -684,6 +689,9 @@
 
 # Turn off fpu, disable interrupts, set kernel mode kernel mode, clear exception level.
 	and	t0, a0, ~(SR_COP_1_BIT | SR_EXL | SR_INT_ENAB | SR_KSU_MASK)
+#ifdef TARGET_OCTEON
+	or      t0, t0, (MIPS_SR_KX | MIPS_SR_SX | MIPS_SR_UX)
+#endif	
 	mtc0	t0, COP_0_STATUS_REG
 	ITLBNOPFIX
 	addu	a0, k1, U_PCB_REGS
@@ -767,7 +775,7 @@
 #ifdef TARGET_OCTEON
 	and k0, k0, ~(MIPS_SR_KX | MIPS_SR_SX | MIPS_SR_UX)
 #endif
-	or  k0, k0, MIPS_SR_INT_IE
+	or  k0, k0, (MIPS_SR_INT_IE)
 	.set	noat
 	RESTORE_U_PCB_REG(AT, AST, k1)
 



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