From owner-p4-projects@FreeBSD.ORG Tue Mar 4 12:18:11 2008 Return-Path: Delivered-To: p4-projects@freebsd.org Received: by hub.freebsd.org (Postfix, from userid 32767) id CCBE11065673; Tue, 4 Mar 2008 12:18:10 +0000 (UTC) Delivered-To: perforce@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id 8C89A106566B for ; Tue, 4 Mar 2008 12:18:10 +0000 (UTC) (envelope-from rrs@cisco.com) Received: from repoman.freebsd.org (repoman.freebsd.org [IPv6:2001:4f8:fff6::29]) by mx1.freebsd.org (Postfix) with ESMTP id 84AE28FC21 for ; Tue, 4 Mar 2008 12:18:10 +0000 (UTC) (envelope-from rrs@cisco.com) Received: from repoman.freebsd.org (localhost [127.0.0.1]) by repoman.freebsd.org (8.14.1/8.14.1) with ESMTP id m24CIAsC091834 for ; Tue, 4 Mar 2008 12:18:10 GMT (envelope-from rrs@cisco.com) Received: (from perforce@localhost) by repoman.freebsd.org (8.14.1/8.14.1/Submit) id m24CIAU9091832 for perforce@freebsd.org; Tue, 4 Mar 2008 12:18:10 GMT (envelope-from rrs@cisco.com) Date: Tue, 4 Mar 2008 12:18:10 GMT Message-Id: <200803041218.m24CIAU9091832@repoman.freebsd.org> X-Authentication-Warning: repoman.freebsd.org: perforce set sender to rrs@cisco.com using -f From: "Randall R. Stewart" To: Perforce Change Reviews Cc: Subject: PERFORCE change 136809 for review X-BeenThere: p4-projects@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: p4 projects tree changes List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 04 Mar 2008 12:18:11 -0000 http://perforce.freebsd.org/chv.cgi?CH=136809 Change 136809 by rrs@rrs-mips2-jnpr on 2008/03/04 12:17:53 Carefully disable interrupts, not just blindly stuff 0 into the SR, instead, mask in the old value with INT_IE and INT_EXL off. Affected files ... .. //depot/projects/mips2-jnpr/src/sys/mips/mips/exception.S#20 edit Differences ... ==== //depot/projects/mips2-jnpr/src/sys/mips/mips/exception.S#20 (text+ko) ==== @@ -263,17 +263,22 @@ #ifdef TARGET_OCTEON #define CLEAR_STATUS \ mfc0 a0, COP_0_STATUS_REG ;\ - li a2, ~(SR_INT_ENAB | SR_EXL | SR_KSU_MASK) ;\ - and a0, a0, a2 ;\ - or a0, a0, (MIPS_SR_KX | MIPS_SR_SX | MIPS_SR_UX) ; \ + li a2, (MIPS_SR_KX | MIPS_SR_SX | MIPS_SR_UX) ; \ + or a0, a0, a2 ; \ + li a2, ~(MIPS_SR_INT_IE|MIPS_SR_EXL) ; \ + and a0, a0, a2 ; \ mtc0 a0, COP_0_STATUS_REG #else #define CLEAR_STATUS \ - mtc0 zero, COP_0_STATUS_REG + mfc0 a0, COP_0_STATUS_REG ;\ + li a2, ~(MIPS_SR_INT_IE|MIPS_SR_EXL) ; \ + and a0, a0, a2 ; \ + mtc0 a0, COP_0_STATUS_REG #endif #define SAVE_CPU \ SAVE_REG(AT, AST, sp) ;\ + .set at ; \ SAVE_REG(v0, V0, sp) ;\ SAVE_REG(v1, V1, sp) ;\ SAVE_REG(a0, A0, sp) ;\ @@ -331,6 +336,7 @@ mtlo t0 ;\ mthi t1 ;\ _MTC0 v0, COP_0_EXC_PC ;\ + .set noat ; \ RESTORE_REG(AT, AST, sp) ;\ RESTORE_REG(v0, V0, sp) ;\ RESTORE_REG(v1, V1, sp) ;\ @@ -545,8 +551,7 @@ #ifdef TARGET_OCTEON and k0, k0, ~(MIPS_SR_KX | MIPS_SR_SX | MIPS_SR_UX) #endif - or k0, k0, MIPS_SR_INT_IE - + or k0, k0, (MIPS_SR_INT_IE) .set noat RESTORE_U_PCB_REG(AT, AST, k1) @@ -587,6 +592,7 @@ * Save the relevant kernel registers onto the stack. */ SAVE_CPU + /* * Call the interrupt handler. */ @@ -603,7 +609,6 @@ RESTORE_CPU sync eret - .set at END(MipsKernIntr) @@ -684,6 +689,9 @@ # Turn off fpu, disable interrupts, set kernel mode kernel mode, clear exception level. and t0, a0, ~(SR_COP_1_BIT | SR_EXL | SR_INT_ENAB | SR_KSU_MASK) +#ifdef TARGET_OCTEON + or t0, t0, (MIPS_SR_KX | MIPS_SR_SX | MIPS_SR_UX) +#endif mtc0 t0, COP_0_STATUS_REG ITLBNOPFIX addu a0, k1, U_PCB_REGS @@ -767,7 +775,7 @@ #ifdef TARGET_OCTEON and k0, k0, ~(MIPS_SR_KX | MIPS_SR_SX | MIPS_SR_UX) #endif - or k0, k0, MIPS_SR_INT_IE + or k0, k0, (MIPS_SR_INT_IE) .set noat RESTORE_U_PCB_REG(AT, AST, k1)