From owner-svn-src-stable-8@FreeBSD.ORG Thu Nov 11 02:37:50 2010 Return-Path: Delivered-To: svn-src-stable-8@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id C0CF0106564A; Thu, 11 Nov 2010 02:37:50 +0000 (UTC) (envelope-from kevlo@FreeBSD.org) Received: from svn.freebsd.org (svn.freebsd.org [IPv6:2001:4f8:fff6::2c]) by mx1.freebsd.org (Postfix) with ESMTP id 950BA8FC15; Thu, 11 Nov 2010 02:37:50 +0000 (UTC) Received: from svn.freebsd.org (localhost [127.0.0.1]) by svn.freebsd.org (8.14.3/8.14.3) with ESMTP id oAB2boGY044792; Thu, 11 Nov 2010 02:37:50 GMT (envelope-from kevlo@svn.freebsd.org) Received: (from kevlo@localhost) by svn.freebsd.org (8.14.3/8.14.3/Submit) id oAB2bowa044790; Thu, 11 Nov 2010 02:37:50 GMT (envelope-from kevlo@svn.freebsd.org) Message-Id: <201011110237.oAB2bowa044790@svn.freebsd.org> From: Kevin Lo Date: Thu, 11 Nov 2010 02:37:50 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-stable@freebsd.org, svn-src-stable-8@freebsd.org X-SVN-Group: stable-8 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Cc: Subject: svn commit: r215106 - stable/8/sys/arm/include X-BeenThere: svn-src-stable-8@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: SVN commit messages for only the 8-stable src tree List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 11 Nov 2010 02:37:50 -0000 Author: kevlo Date: Thu Nov 11 02:37:50 2010 New Revision: 215106 URL: http://svn.freebsd.org/changeset/base/215106 Log: MFC r214972,r215031: - Intel IXP425 SoC is based on the ARMv5TE architecture - Minor cosmetic changes Modified: stable/8/sys/arm/include/cpuconf.h Modified: stable/8/sys/arm/include/cpuconf.h ============================================================================== --- stable/8/sys/arm/include/cpuconf.h Thu Nov 11 00:29:19 2010 (r215105) +++ stable/8/sys/arm/include/cpuconf.h Thu Nov 11 02:37:50 2010 (r215106) @@ -68,7 +68,7 @@ */ #if (defined(CPU_ARM7TDMI) || defined(CPU_ARM8) || defined(CPU_ARM9) || \ defined(CPU_SA110) || defined(CPU_SA1100) || defined(CPU_SA1110) || \ - defined(CPU_IXP12X0) || defined(CPU_XSCALE_IXP425)) + defined(CPU_IXP12X0)) #define ARM_ARCH_4 1 #else #define ARM_ARCH_4 0 @@ -77,7 +77,7 @@ #if (defined(CPU_ARM9E) || defined(CPU_ARM10) || \ defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \ defined(CPU_XSCALE_80219) || defined(CPU_XSCALE_81342) || \ - defined(CPU_XSCALE_PXA2X0)) + defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425)) #define ARM_ARCH_5 1 #else #define ARM_ARCH_5 0 @@ -138,9 +138,9 @@ #define ARM_MMU_SA1 0 #endif -#if(defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \ - defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) || \ - defined(CPU_XSCALE_80219)) || defined(CPU_XSCALE_81342) +#if (defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \ + defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) || \ + defined(CPU_XSCALE_80219) || defined(CPU_XSCALE_81342)) #define ARM_MMU_XSCALE 1 #else #define ARM_MMU_XSCALE 0 @@ -159,7 +159,7 @@ */ #if (defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \ - defined(CPU_XSCALE_80219)) || defined(CPU_XSCALE_81342) + defined(CPU_XSCALE_80219) || defined(CPU_XSCALE_81342)) #define ARM_XSCALE_PMU 1 #else #define ARM_XSCALE_PMU 0