Date: Fri, 12 Mar 2004 11:29:47 -0800 (PST) From: Juli Mallett <jmallett@FreeBSD.org> To: Perforce Change Reviews <perforce@freebsd.org> Subject: PERFORCE change 48809 for review Message-ID: <200403121929.i2CJTlZM061317@repoman.freebsd.org>
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http://perforce.freebsd.org/chv.cgi?CH=48809 Change 48809 by jmallett@jmallett_oingo on 2004/03/12 11:29:37 Handle TLB Reload requirements for TLBS/TLBL in the case where half the pair is in the TLB, but tlb_enter didn't update the TLB. I like this. I don't like what I did to the code, but the comments go in to that more than I should here. Affected files ... .. //depot/projects/mips/sys/mips/mips/exception.S#19 edit Differences ... ==== //depot/projects/mips/sys/mips/mips/exception.S#19 (text+ko) ==== @@ -23,7 +23,7 @@ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * - * $P4: //depot/projects/mips/sys/mips/mips/exception.S#18 $ + * $P4: //depot/projects/mips/sys/mips/mips/exception.S#19 $ */ #include "opt_ddb.h" @@ -49,8 +49,8 @@ ExceptionHandlerTable: .dword GenericException /* Int */ .dword GenericException /* TLBMod */ - .dword XTLBMissVector /* TLBL */ - .dword XTLBMissVector /* TLBS */ + .dword XTLBReload /* TLBL */ + .dword XTLBReload /* TLBS */ .dword GenericException /* AdEL */ .dword GenericException /* AdES */ .dword GenericException /* IBE */ @@ -168,6 +168,65 @@ /* * XXX kernel only. For now that makes sense. */ +LEAF(XTLBReload) + .set noat + tlbp + nop + mfc0 k0, MIPS_COP_0_TLB_INDEX + nop + blezl k0, 1f + nop + /* We have an index, it's a reload. XXX Copying from XTLBMiss + * because I can't make that tlbwi, unless I pick a random + * Index for it, and somehow that doesn't feel good. XXX2 Note + * that TLBS is just a degenerate case of Mod, it's where the + * mapping needs set up into the TLB, as well, cause it was + * created after the other entry in the TLB, and is invalid + * in the TLB. It actually could go through the Mod code and + * work fine, but I'd rather take two exceptions. The other + * side of this argument is that tlb_enter should update the + * TLB. This is possibly true, but I like lazy loading, since + * we have to reload a lot in theory, anyway. + */ + dmfc0 k0, MIPS_COP_0_BAD_VADDR + dli k1, MIPS_XKSEG_START + tltu k0, k1 + dsubu k0, k1 + /* + * Shift right logical to get a page index, but leaving + * enough bits to index an array of 64 bit values, plus + * align for the even/odd TLB stuff. + */ + dsrl k0, PAGE_SHIFT + 1 + dsll k0, 3 + 1 + dla k1, kptmap + /* + * Find the page table, and index it. + */ + ld k1, 0(k1) + addu k1, k0 + /* + * Write the pair. + */ + ld k0, 0(k1) /* Even PTE. */ + ld k1, 8(k1) /* Odd PTE. */ + /* + * Write TLB entry. + */ + dmtc0 k0, MIPS_COP_0_TLB_LO0 + dmtc0 k1, MIPS_COP_0_TLB_LO1 + nop + tlbwi + eret + /* Not in TLB, it's a miss. */ +1: j XTLBMissVector + nop + .set at +END(XTLBReload) + +/* + * XXX kernel only. For now that makes sense. + */ LEAF(XTLBMissVector) .set noat dmfc0 k0, MIPS_COP_0_BAD_VADDR
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