Date: Tue, 27 Mar 2012 22:44:54 -0700 From: Adrian Chadd <adrian@freebsd.org> To: freebsd-mips@freebsd.org Subject: [patch] enable mdio port 1, remove phy mask hard coding Message-ID: <CAJ-VmomfLdqv=5_wQmB%2BxNH6mKh6OieTAH4auS232ZFHKeHmzQ@mail.gmail.com>
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--047d7b15a12f5e162504bc471bb1 Content-Type: text/plain; charset=ISO-8859-1 Hi all, This patch does a few things: * it adds mdio port 1 (from MAC1/arge1); * it removes the hard-coded assumption that arge0/arge1 share the same mdio bus, which I believe is only relevant for AR71xx; * it removes phymask from the arge config; * it introduces a new configuration parameter, "multiphy", which binds the port to the fake phy. The existing code does this if phymask has >1 bit set. This makes it absolutely obvious. Since ar724x CPUs have >1 MDIO bus, we have to do this work to support the switch phys that ship with these things. This now raises the issue of how to handle switch PHYs and normal PHYs on alternate busses. For example, the PB47 reference board has the PHY for arge1 hang off the only MDIO bus on the board (AR7161) - which is MDIO 0. It's about time we fixed this stuff. I want to push in the switch code from juli/pat/ray/stb now. adrian --047d7b15a12f5e162504bc471bb1 Content-Type: text/x-patch; charset=US-ASCII; name="head-arge-enable-mii1.diff" Content-Disposition: attachment; filename="head-arge-enable-mii1.diff" Content-Transfer-Encoding: base64 X-Attachment-Id: f_h0by5nb20 SW5kZXg6IHN5cy9taXBzL2F0aGVyb3MvaWZfYXJnZS5jCj09PT09PT09PT09PT09PT09PT09PT09 PT09PT09PT09PT09PT09PT09PT09PT09PT09PT09PT09PT09PT09PT09PT0KLS0tIHN5cy9taXBz L2F0aGVyb3MvaWZfYXJnZS5jCShyZXZpc2lvbiAyMzM1MzEpCisrKyBzeXMvbWlwcy9hdGhlcm9z L2lmX2FyZ2UuYwkod29ya2luZyBjb3B5KQpAQCAtMjQxLDkgKzI0MSw5IEBACiAJdWludDhfdAkJ CWVhZGRyW0VUSEVSX0FERFJfTEVOXTsKIAlzdHJ1Y3QgaWZuZXQJCSppZnA7CiAJc3RydWN0IGFy Z2Vfc29mdGMJKnNjOwotCWludAkJCWVycm9yID0gMCwgcmlkLCBwaHltYXNrOworCWludAkJCWVy cm9yID0gMCwgcmlkOwogCXVpbnQzMl90CQlyZWcsIHJuZDsKLQlpbnQJCQlpc19iYXNlX21hY19l bXB0eSwgaSwgcGh5c190b3RhbDsKKwlpbnQJCQlpc19iYXNlX21hY19lbXB0eSwgaSwgcmV0LCBt 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