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From: Konstantin Belousov <kib@FreeBSD.org>
Date: Sun, 19 Apr 2015 08:31:27 +0000 (UTC)
To: src-committers@freebsd.org, svn-src-all@freebsd.org,
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Subject: svn commit: r281732 - stable/10/sys/dev/acpica
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Author: kib
Date: Sun Apr 19 08:31:26 2015
New Revision: 281732
URL: https://svnweb.freebsd.org/changeset/base/281732

Log:
  MFC r281462:
  Define capabilities bits from the revision 007 of the document 302223.

Modified:
  stable/10/sys/dev/acpica/acpivar.h
Directory Properties:
  stable/10/   (props changed)

Modified: stable/10/sys/dev/acpica/acpivar.h
==============================================================================
--- stable/10/sys/dev/acpica/acpivar.h	Sun Apr 19 08:30:13 2015	(r281731)
+++ stable/10/sys/dev/acpica/acpivar.h	Sun Apr 19 08:31:26 2015	(r281732)
@@ -185,7 +185,7 @@ extern struct mtx			acpi_mutex;
  * Various features and capabilities for the acpi_get_features() method.
  * In particular, these are used for the ACPI 3.0 _PDC and _OSC methods.
  * See the Intel document titled "Intel Processor Vendor-Specific ACPI",
- * number 302223-005.
+ * number 302223-007.
  */
 #define	ACPI_CAP_PERF_MSRS	(1 << 0)  /* Intel SpeedStep PERF_CTL MSRs */
 #define	ACPI_CAP_C1_IO_HALT	(1 << 1)  /* Intel C1 "IO then halt" sequence */
@@ -198,6 +198,9 @@ extern struct mtx			acpi_mutex;
 #define	ACPI_CAP_SMP_C1_NATIVE	(1 << 8)  /* MP C1 support other than halt */
 #define	ACPI_CAP_SMP_C3_NATIVE	(1 << 9)  /* MP C2 and C3 support */
 #define	ACPI_CAP_PX_HW_COORD	(1 << 11) /* Intel P-state HW coordination */
+#define	ACPI_CAP_INTR_CPPC	(1 << 12) /* Native Interrupt Handling for
+	     Collaborative Processor Performance Control notifications */
+#define	ACPI_CAP_HW_DUTY_C	(1 << 13) /* Hardware Duty Cycling */
 
 /*
  * Quirk flags.