Date: Mon, 3 Apr 2017 16:14:02 +0200 From: Zbigniew Bodek <zbb@semihalf.com> To: Andrew Turner <andrew@fubar.geek.nz> Cc: Marcin Wojtas <mw@semihalf.com>, Adrian Chadd <adrian.chadd@gmail.com>, "freebsd-arm@freebsd.org" <freebsd-arm@freebsd.org> Subject: Re: Coherent bus_dma for ARMv7 Message-ID: <CAG7dG%2BxhB5J-sHSCg9-03776PO=SHDTuESpfy76GbeNOc8mziw@mail.gmail.com> In-Reply-To: <0EA39E6B-3460-45B9-8247-CB6CC8631C5F@fubar.geek.nz> References: <CAPv3WKejupH4JG1=_XV6PknnKifxbF0qoVubtMRVtZWEoBZ7xg@mail.gmail.com> <CAPv3WKcG_Y=5zPk-2vGbQfCpiNcWvuUymY8EHRnWsM2FUzcG4Q@mail.gmail.com> <CAJ-Vmo=UC9K3e0TJGU86JZ6npzRevjpC3UEwgWrrh9mjCELKMg@mail.gmail.com> <CAPv3WKez8ZP=xONvPWGiyL5pQDKO4wGF_qQn=eT1S_LzrGJ74g@mail.gmail.com> <0EA39E6B-3460-45B9-8247-CB6CC8631C5F@fubar.geek.nz>
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2017-04-03 15:37 GMT+02:00 Andrew Turner <andrew@fubar.geek.nz>: > > > On 3 Apr 2017, at 14:16, Marcin Wojtas <mw@semihalf.com> wrote: > > > > Hi Adrian, > > > > Frankly we are not such experts in armv6 bus_dma, which looks more > > complicated than one in arm64, so we thought it's much safer no to mix > > the two solutions and leave for the user a single switch to decide, > > which one to pick. Afaik Andrew Turner did the oposite for arm64 > > (implement not coherent solution on top of coherent bus_dma), however > > I'm not sure if it's possible here in an easy way - there's also > > pretty significant risk of regression for all platforms. Please let me > > know your opinion. Do you think some sort of update of armv6 is > > doable? > > I don=E2=80=99t see any reason to think it would be difficult to add supp= ort for > coherent hardware to the existing armv6 busdma code. It=E2=80=99s mostly = skipping > cache operations based on a flag in the dam tag. > > Andrew > Hello Andrew, I don't think anyone uses flags related to DMA coherency in bus_dma_tag_create. Nevertheless, for coherent platforms we want bus_dma to always map DMA memory as normal WBWA regardless of the flags passed to create a bus_dma MAP. For example, we don't want to perform any synchronization and we want to have the cacheable memory regardless of BUS_DMA_COHERENT flag used. Otherwise the performance improvement will apply only to those drivers that dare to use BUS_DMA_COHERENT flag and very few of them does that. In other words, what is the point of having coherent DMA if you do cache maintenance anyway? Another thing is that we need specific changes to the CPU configuration and mappings (SMP bit enabled + Shared attribute enabled) but this is for separate discussion. Kind regards zbb
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