Date: Thu, 24 May 2012 13:03:00 -0400 From: "cherry@zyx.in" <cherry@zyx.in> To: cherry@freebsd.org, src-committers@freebsd.org, svn-src-projects@freebsd.org Subject: mmu_map.h review/justification - was => RE: svn commit: r235904 - in projects/amd64_xen_pv/sys: amd64/xen conf Message-ID: <380-2201254241730954@M2W103.mail2web.com>
next in thread | raw e-mail | index | archive | help
Hi, Apologies for the top-post - I'm having mail client difficulties at the moment=2E I have recieved private feedback about the contents of the commit log message, so I thought I would address them here, and keep it in mind for future commits=2E The main question is "rationale/justification" for the a= pi in the diff below, and I will try to address that here: Facts: - The x86 MMU hardware works with a hierarchical page table=2E Pages in th= e hierarchy are referred to each other by physical addresses=2E - The processor itself however accesses all memory via virtual addresses=2E= What this means is that in order for the kernel to manipulate page tables entries, it needs to have the pages in the hierarchy themselves to be mapped into its virtual address space=2E However, this requires that the p= age tables be setup already to facilitate this - clearly a bootstrap problem=2E= In order to address this problem, I've attempted to come up with an API that is easy to use, who's objective is to do "whatever it takes" to the MMU, to make the pages in the physical hierarchy visible to the kernel virtual address space=2E The use of the api is very intuitive=2E One basically says to it: "Do whatever it takes to make the mapping va->pa viable"=2E On x86, this basically means setting up the page table hierarchy (if this has not already been done) and providing a means for the caller to inspect the contents of the backing pages=2E On other architectures, with software TLB= s, for eg:, I would envisage the implementation returning a direct mapped segment offset to the page, so that the caller can then insert this into the soft TLB=2E Admittedly I haven't given too much thought to it beyond t= hat - I've only attempted to not restrict the API design to the x86 paging architecture alone, as far as is possible=2E In order for the implementation to do "whatever it takes", the caller is provided with a set of callbacks that allocate resources if required=2E On= x86, the callbacks need to make sure that the returned memory which will b= e used for backing page tables is already mapped into the kernel address space=2E On xen, we have the additional requirement that page tables are n= ot mapped in into the KVA space as writeable pages=2E On the upside, xen provides us with about 512kb of already mapped in memory at boot - so we just lop off chunks of it via vallocpages() (see pmap=2Ec)=2E That's it, really=2E It's a fairly intuitive api once the background is in place=2E O= n the down side, it's bound to be ridiculously unoptimal, and I imagine there ar= e other subsystems already in the kernel which provide this functionality - albeit unavailable at boot ( the reason I wrote this api )=2E As I get alo= ng with the port, I will make a decision ( open to feedback here ) about the future of the api within the amd64/xen subdirectory=2E I don't expect this api to be used outside of the x86 architecture, or outside of the amd64/xen port at this point, but I've written it with a view to it being useful, if possible=2E I hope that was a useful explanation=2E Many Thanks, Cherry=2E Original Message: ----------------- From: Cherry G=2E Mathew cherry@FreeBSD=2Eorg Date: Thu, 24 May 2012 12:02:11 +0000 (UTC) To: src-committers@freebsd=2Eorg, svn-src-projects@freebsd=2Eorg Subject: svn commit: r235904 - in projects/amd64=5Fxen=5Fpv/sys: amd64/xen= conf Author: cherry Date: Thu May 24 12:02:10 2012 New Revision: 235904 URL: http://svn=2Efreebsd=2Eorg/changeset/base/235904 Log: This API is an attempt to abstract the MMU state in an MI fashion=2E It = is heavily wip and may or may not go away, from amd64/ depending on how thing= s go with the direct mapped implementation Added: projects/amd64=5Fxen=5Fpv/sys/amd64/xen/mmu=5Fmap=2Ec projects/amd64=5Fxen=5Fpv/sys/amd64/xen/mmu=5Fmap=2Eh Modified: projects/amd64=5Fxen=5Fpv/sys/conf/files=2Eamd64 Added: projects/amd64=5Fxen=5Fpv/sys/amd64/xen/mmu=5Fmap=2Ec =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D =3D=3D --- /dev/null=0900:00:00 1970=09(empty, because file is newly added) +++ projects/amd64=5Fxen=5Fpv/sys/amd64/xen/mmu=5Fmap=2Ec=09Thu May 24 12:= 02:10 2012=09(r235904) @@ -0,0 +1,389 @@ +/* $FreeBSD$ */ +/*- + * Copyright (c) 2011-2012 Spectra Logic Corporation + * All rights reserved=2E + * + * This software was developed by Cherry G=2E Mathew <cherry@FreeBSD=2Eor= g> + * under sponsorship from Spectra Logic Corporation=2E + *=20 + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1=2E Redistributions of source code must retain the above copyright + * notice, this list of conditions, and the following disclaimer, + * without modification=2E + * 2=2E Redistributions in binary form must reproduce at minimum a discla= imer + * substantially similar to the "NO WARRANTY" disclaimer below + * ("Disclaimer") and any redistribution must be conditioned upon + * including a substantially similar Disclaimer requirement for furthe= r + * binary redistribution=2E + * + * NO WARRANTY + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED=2E IN NO EVENT SHALL THE COPYRIGHT= + * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOOD= S + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGES=2E + */ + + +/* + * This file implements the API that manages the page table + * hierarchy for the amd64 Xen pmap=2E + */ +#include <sys/cdefs=2Eh> +=5F=5FFBSDID("$FreeBSD$"); + +#include "opt=5Fcpu=2Eh" +#include "opt=5Fpmap=2Eh" +#include "opt=5Fsmp=2Eh" + + +#include <sys/param=2Eh> +#include <sys/systm=2Eh> +#include <sys/types=2Eh> + +#include <vm/vm=2Eh> +#include <vm/vm=5Fparam=2Eh> +#include <vm/pmap=2Eh> + +#include <xen/hypervisor=2Eh> +#include <machine/xen/xenvar=2Eh> + +#include <amd64/xen/mmu=5Fmap=2Eh> + +static int +pml4t=5Findex(vm=5Foffset=5Ft va) +{ +=09/* amd64 sign extends 48th bit and upwards */ +=09const uint64=5Ft SIGNMASK =3D (1UL << 48) - 1; +=09va &=3D SIGNMASK; /* Remove sign extension */ + +=09return (va >> PML4SHIFT);=20 +} + +static int +pdpt=5Findex(vm=5Foffset=5Ft va) +{ +=09/* amd64 sign extends 48th bit and upwards */ +=09const uint64=5Ft SIGNMASK =3D (1UL << 48) - 1; +=09va &=3D SIGNMASK; /* Remove sign extension */ + +=09return ((va & PML4MASK) >> PDPSHIFT); +} + +static int +pdt=5Findex(vm=5Foffset=5Ft va) +{ +=09/* amd64 sign extends 48th bit and upwards */ +=09const uint64=5Ft SIGNMASK =3D (1UL << 48) - 1; +=09va &=3D SIGNMASK; /* Remove sign extension */ + +=09return ((va & PDPMASK) >> PDRSHIFT); +} + +/*=20 + * The table get functions below assume that a table cannot exist at + * address 0 + */ +static pml4=5Fentry=5Ft * +pmap=5Fget=5Fpml4t(struct pmap *pm) +{ +=09KASSERT(pm !=3D NULL, +=09=09("NULL pmap passed in!\n")); + +=09pml4=5Fentry=5Ft *pm=5Fpml4 =3D pm->pm=5Fpml4; +=09 +=09KASSERT(pm=5Fpml4 !=3D NULL, +=09=09("pmap has NULL pml4!\n")); + +=09return pm->pm=5Fpml4; +} + +/* Returns physical address */ +static vm=5Fpaddr=5Ft +pmap=5Fget=5Fpdpt(vm=5Foffset=5Ft va, pml4=5Fentry=5Ft *pml4t) +{ +=09pml4=5Fentry=5Ft pml4e; + +=09KASSERT(va <=3D VM=5FMAX=5FKERNEL=5FADDRESS, +=09=09("invalid address requested")); +=09KASSERT(pml4t !=3D 0, ("pml4t cannot be zero")); + +=09pml4e =3D pml4t[pml4t=5Findex(va)]; + +=09if (!(pml4e & PG=5FV)) { +=09=09return 0; +=09} + +=09return xpmap=5Fmtop(pml4e & PG=5FFRAME); +} + +/* Returns physical address */ +static vm=5Fpaddr=5Ft +pmap=5Fget=5Fpdt(vm=5Foffset=5Ft va, pdp=5Fentry=5Ft *pdpt) +{ +=09pdp=5Fentry=5Ft pdpe; + +=09KASSERT(va <=3D VM=5FMAX=5FKERNEL=5FADDRESS, +=09=09("invalid address requested")); +=09KASSERT(pdpt !=3D 0, ("pdpt cannot be zero")); + +=09pdpe =3D pdpt[pdpt=5Findex(va)]; + +=09if (!(pdpe & PG=5FV)) { +=09=09return 0; +=09} + +=09return xpmap=5Fmtop(pdpe & PG=5FFRAME); +} + +/* Returns physical address */ +static vm=5Fpaddr=5Ft +pmap=5Fget=5Fpt(vm=5Foffset=5Ft va, pd=5Fentry=5Ft *pdt) +{ +=09pd=5Fentry=5Ft pdte; + +=09KASSERT(va <=3D VM=5FMAX=5FKERNEL=5FADDRESS, +=09=09("invalid address requested")); + +=09KASSERT(pdt !=3D 0, ("pdt cannot be zero")); + +=09pdte =3D pdt[pdt=5Findex(va)]; + +=09if (!(pdte & PG=5FV)) { +=09=09return 0; +=09} + +=09return xpmap=5Fmtop(pdte & PG=5FFRAME); +} + +/*=20 + * This structure defines the 4 indices that a given virtual + * address lookup would traverse=2E + * + * Note: this structure is opaque to API customers=2E Callers give us an + * untyped array which is marshalled/unmarshalled inside of the + * stateful api=2E + */ + +static const uint64=5Ft SANE =3D 0xcafebabe; + +struct mmu=5Fmap=5Findex { +=09pml4=5Fentry=5Ft *pml4t; /* Page Map Level 4 Table */ +=09pdp=5Fentry=5Ft *pdpt; /* Page Directory Pointer Table */ +=09pd=5Fentry=5Ft *pdt; /* Page Directory Table */ +=09pt=5Fentry=5Ft *pt; /* Page Table */ + +=09struct mmu=5Fmap=5Fmbackend ptmb; /* Backend info */ + +=09uint32=5Ft sanity; /* 32 bit (for alignment) magic XXX: +=09=09=09 * Make optional on DEBUG */ +}; + +size=5Ft +mmu=5Fmap=5Ft=5Fsize(void) +{ +=09return sizeof (struct mmu=5Fmap=5Findex); +} + +void +mmu=5Fmap=5Ft=5Finit(void *addr, struct mmu=5Fmap=5Fmbackend *mb) +{ +=09KASSERT((addr !=3D NULL) && (mb !=3D NULL), ("NULL args given!")); +=09struct mmu=5Fmap=5Findex *pti =3D addr; +=09KASSERT(pti->sanity !=3D SANE, ("index initialised twice!")); +=09KASSERT(mb->alloc !=3D NULL && +=09=09mb->ptov !=3D NULL && +=09=09mb->vtop !=3D NULL,=20 +=09=09("initialising with pre-registered alloc routine active")); + +=09pti->ptmb =3D *mb; + +=09/* Backend page allocation should provide default VA mapping */ +=09pti->sanity =3D SANE; +} + +void mmu=5Fmap=5Ft=5Ffini(void *addr) +{ +=09KASSERT(addr !=3D NULL, ("NULL args given!")); + +=09struct mmu=5Fmap=5Findex *pti =3D addr; +=09KASSERT(pti->sanity =3D=3D SANE, ("Uninitialised index cookie used"));= +=09struct mmu=5Fmap=5Fmbackend *mb =3D &pti->ptmb; + +=09pti->sanity =3D 0; + +=09if (mb->free !=3D NULL) { +=09=09/* XXX: go through PT hierarchy and free + unmap +=09=09 * unused tables */=20 +=09} +} + +pd=5Fentry=5Ft * +mmu=5Fmap=5Fpml4t(void *addr) +{ +=09KASSERT(addr !=3D NULL, ("NULL args given!")); +=09struct mmu=5Fmap=5Findex *pti =3D addr; + +=09KASSERT(pti->sanity =3D=3D SANE, ("Uninitialised index cookie used"));= + +=09return pti->pml4t; +} + +pd=5Fentry=5Ft * +mmu=5Fmap=5Fpdpt(void *addr) +{ +=09KASSERT(addr !=3D NULL, ("NULL args given!")); +=09struct mmu=5Fmap=5Findex *pti =3D addr; + +=09KASSERT(pti->sanity =3D=3D SANE, ("Uninitialised index cookie used"));= + +=09return pti->pdpt; +} + +pd=5Fentry=5Ft * +mmu=5Fmap=5Fpdt(void *addr) +{ +=09KASSERT(addr !=3D NULL, ("NULL args given!")); +=09struct mmu=5Fmap=5Findex *pti =3D addr; + +=09KASSERT(pti->sanity =3D=3D SANE, ("Uninitialised index cookie used"));= + +=09return pti->pdt; +} + +pd=5Fentry=5Ft * +mmu=5Fmap=5Fpt(void *addr) +{ +=09KASSERT(addr !=3D NULL, ("NULL args given!")); +=09struct mmu=5Fmap=5Findex *pti =3D addr; + +=09KASSERT(pti->sanity =3D=3D SANE, ("Uninitialised index cookie used"));= + +=09return pti->pt; +} + +bool +mmu=5Fmap=5Finspect=5Fva(struct pmap *pm, void *addr, vm=5Foffset=5Ft va)= +{ +=09KASSERT(addr !=3D NULL && pm !=3D NULL, ("NULL arg(s) given")); + +=09struct mmu=5Fmap=5Findex *pti =3D addr; +=09KASSERT(pti->sanity =3D=3D SANE, ("Uninitialised index cookie used"));= + +=09vm=5Fpaddr=5Ft pt; + +=09pti->pml4t =3D pmap=5Fget=5Fpml4t(pm); + +=09pt =3D pmap=5Fget=5Fpdpt(va, pti->pml4t); + +=09if (pt =3D=3D 0) { +=09=09return false; +=09} else { +=09=09pti->pdpt =3D (pdp=5Fentry=5Ft *) pti->ptmb=2Eptov(pt); +=09} + +=09pt =3D pmap=5Fget=5Fpdt(va, pti->pdpt); + +=09if (pt =3D=3D 0) { +=09=09return false; +=09} else { +=09=09pti->pdt =3D (pd=5Fentry=5Ft *) pti->ptmb=2Eptov(pt); +=09} + +=09pt =3D pmap=5Fget=5Fpt(va, pti->pdt); + +=09if (pt =3D=3D 0) { +=09=09return false; +=09} else { +=09=09pti->pt =3D (pt=5Fentry=5Ft *)pti->ptmb=2Eptov(pt); +=09} + +=09return true; +} +extern uint64=5Ft xenstack; /* The stack Xen gives us at boot */ +void +mmu=5Fmap=5Fhold=5Fva(struct pmap *pm, void *addr, vm=5Foffset=5Ft va) +{ +=09KASSERT(addr !=3D NULL && pm !=3D NULL, ("NULL arg(s) given")); + +=09struct mmu=5Fmap=5Findex *pti =3D addr; +=09KASSERT(pti->sanity =3D=3D SANE, ("Uninitialised index cookie used"));= + +=09vm=5Fpaddr=5Ft pt; + +=09pti->pml4t =3D pmap=5Fget=5Fpml4t(pm); + +=09pt =3D pmap=5Fget=5Fpdpt(va, pti->pml4t); + +=09if (pt =3D=3D 0) { +=09=09pml4=5Fentry=5Ft *pml4tep; +=09=09vm=5Fpaddr=5Ft pml4tep=5Fma; +=09=09pml4=5Fentry=5Ft pml4te; + +=09=09pti->pdpt =3D (pdp=5Fentry=5Ft *)pti->ptmb=2Ealloc(PAGE=5FSIZE); + +=09=09pml4tep =3D &pti->pml4t[pml4t=5Findex(va)]; +=09=09pml4tep=5Fma =3D xpmap=5Fptom(pti->ptmb=2Evtop((vm=5Foffset=5Ft)pml= 4tep)); +=09=09pml4te =3D xpmap=5Fptom(pti->ptmb=2Evtop((vm=5Foffset=5Ft)pti->pdpt= )) | PG=5FRW | PG=5FV | PG=5FU; /* XXX: revisit flags */ +=09=09xen=5Fqueue=5Fpt=5Fupdate(pml4tep=5Fma, pml4te); + +=09} else { +=09=09pti->pdpt =3D (pdp=5Fentry=5Ft *) pti->ptmb=2Eptov(pt); +=09} + +=09pt =3D pmap=5Fget=5Fpdt(va, pti->pdpt); + +=09if (pt =3D=3D 0) { +=09=09pdp=5Fentry=5Ft *pdptep; +=09=09vm=5Fpaddr=5Ft pdptep=5Fma; +=09=09pdp=5Fentry=5Ft pdpte; + +=09=09pti->pdt =3D (pd=5Fentry=5Ft *)pti->ptmb=2Ealloc(PAGE=5FSIZE); + +=09=09pdptep =3D &pti->pdpt[pdpt=5Findex(va)]; +=09=09pdptep=5Fma =3D xpmap=5Fptom(pti->ptmb=2Evtop((vm=5Foffset=5Ft)pdpt= ep)); +=09=09pdpte =3D xpmap=5Fptom(pti->ptmb=2Evtop((vm=5Foffset=5Ft)pti->pdt))= | PG=5FRW | PG=5FV | PG=5FU; /*=09XXX: revisit flags */ +=09=09xen=5Fqueue=5Fpt=5Fupdate(pdptep=5Fma, pdpte); +=09=09 +=09} else { +=09=09pti->pdt =3D (pd=5Fentry=5Ft *) pti->ptmb=2Eptov(pt); +=09} + +=09pt =3D pmap=5Fget=5Fpt(va, pti->pdt); + +=09if (pt =3D=3D 0) { +=09=09pd=5Fentry=5Ft *pdtep; +=09=09vm=5Fpaddr=5Ft pdtep=5Fma; +=09=09pd=5Fentry=5Ft pdte; + +=09=09pti->pt =3D (pt=5Fentry=5Ft *) pti->ptmb=2Ealloc(PAGE=5FSIZE); + +=09=09pdtep =3D &pti->pdt[pdt=5Findex(va)]; +=09=09pdtep=5Fma =3D xpmap=5Fptom(pti->ptmb=2Evtop((vm=5Foffset=5Ft)pdtep= )); +=09=09pdte =3D xpmap=5Fptom(pti->ptmb=2Evtop((vm=5Foffset=5Ft)pti->pt)) |= PG=5FRW | PG=5FV | PG=5FU; /*=09XXX: revisit flags */ +=09=09xen=5Fqueue=5Fpt=5Fupdate(pdtep=5Fma, pdte); + +=09} else { +=09=09pti->pt =3D (pt=5Fentry=5Ft *) pti->ptmb=2Eptov(pt); +=09} +} + +void +mmu=5Fmap=5Frelease=5Fva(struct pmap *pm, void *addr, vm=5Foffset=5Ft va)= +{ + +=09KASSERT(addr !=3D NULL && pm !=3D NULL, ("NULL arg(s) given")); + +=09struct mmu=5Fmap=5Findex *pti =3D addr; +=09KASSERT(pti->sanity =3D=3D SANE, ("Uninitialised index cookie used"));= + +=09/* XXX: */ +} Added: projects/amd64=5Fxen=5Fpv/sys/amd64/xen/mmu=5Fmap=2Eh =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D =3D=3D --- /dev/null=0900:00:00 1970=09(empty, because file is newly added) +++ projects/amd64=5Fxen=5Fpv/sys/amd64/xen/mmu=5Fmap=2Eh=09Thu May 24 12:= 02:10 2012=09(r235904) @@ -0,0 +1,152 @@ +/* $FreeBSD$ */ +/*- + * Copyright (c) 2011-2012 Spectra Logic Corporation + * All rights reserved=2E + * + * This software was developed by Cherry G=2E Mathew <cherry@FreeBSD=2Eor= g> + * under sponsorship from Spectra Logic Corporation=2E + *=20 + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1=2E Redistributions of source code must retain the above copyright + * notice, this list of conditions, and the following disclaimer, + * without modification=2E + * 2=2E Redistributions in binary form must reproduce at minimum a discla= imer + * substantially similar to the "NO WARRANTY" disclaimer below + * ("Disclaimer") and any redistribution must be conditioned upon + * including a substantially similar Disclaimer requirement for furthe= r + * binary redistribution=2E + * + * NO WARRANTY + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED=2E IN NO EVENT SHALL THE COPYRIGHT= + * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOOD= S + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGES=2E + */ + +#ifndef =5FXEN=5FMMU=5FMAP=5FH=5F +#define =5FXEN=5FMMU=5FMAP=5FH=5F + +#include <sys/types=2Eh> + +#include <machine/pmap=2Eh> + +/*=20 + * + * This API abstracts, in an MI fashion, the paging mechanism of an + * arbitrary CPU architecture as an opaque FSM, which may then be + * subject to inspection in MD ways=2E + * + * Use of this API can have the following effects on the VM system and + * the kernel address space: + * + * - physical memory pages may be allocated=2E + * - physical memory pages may be de-allocated=2E + * - kernel virtual address space may be allocated=2E + * - kernel virtual address space may be de-allocated=2E + * - The page table hierarchy may be modified=2E + * - TLB entries may be invalidated=2E + * + * The API is stateful, and designed around the following principles: + * - Simplicity + * - Object orientation + * - Code reuse=2E + */ + +/*=20 + * We hide the page table structure behind an opaque "index" cookie + * which acts as the "key" to a given va->pa mapping being inspected=2E + */ +typedef void * mmu=5Fmap=5Ft; + +/* + * Memory backend types: + *=20 + * We provide a means to allocate ad-hoc memory/physical page + * requirements to the paging mechanism by means of a "backend" + * alloc function + * + * The memory backend is required to provide physical pages that are + * at least temporarily mapped into the kernel VA space and whose + * contents are thus accessible by a simple pointer indirection from + * within the kernel=2E This requirement may be revoked after conclusion + * of an instance of stateful usage of the API ( See: + * mmu=5Fmap=5Ft=5Ffini() below ), at which point the backend + * implementation is free to unmap any temporary mappings if so + * desired=2E (XXX: review this for non-x86) + * + * Note: Only the mappings may be revoked - any physical pages + * themselves allocated by the backend are considered allocated and + * part of the paging mechanism=2E + */ + +struct mmu=5Fmap=5Fmbackend { /* Callbacks */ + +=09vm=5Foffset=5Ft (*alloc)(size=5Ft); +=09void (*free)(vm=5Foffset=5Ft); /* May be NULL */ + +=09/*=20 +=09 * vtop()/ptov() conversion functions: +=09 * These callbacks typically provide conversions for mapped +=09 * pages allocated via the alloc()/free() callbacks (above)=2E +=09 * The API implementation is free to cache the mappings across +=09 * multiple instances of use; ie; mappings may persist across=20 +=09 * one pair of mmu=5Fmap=5Ft=5Finit()/=2E=2E=5Ffinit() calls=2E +=09 */ +=09vm=5Foffset=5Ft (*ptov)(vm=5Fpaddr=5Ft); +=09vm=5Fpaddr=5Ft (*vtop)(vm=5Foffset=5Ft); +}; + +/*=20 + * Return sizeof (mmu=5Fmap=5Ft) as implemented within the api + * This may then be used to allocate untyped memory for the cookie + * which can then be operated on opaquely behind the API in a machine + * specific manner=2E + */ +size=5Ft mmu=5Fmap=5Ft=5Fsize(void); + +/* + * Initialise the API state to use a specified memory backend=20 + */ +void mmu=5Fmap=5Ft=5Finit(mmu=5Fmap=5Ft, struct mmu=5Fmap=5Fmbackend *); + +/* Conclude this instance of use of the API */ +void mmu=5Fmap=5Ft=5Ffini(mmu=5Fmap=5Ft); + +/* Set "index" cookie state based on va lookup=2E This state may then be + * inspected in MD ways ( See below )=2E Note that every call to the + * following functions can change the state of the backing paging + * mechanism FSM=2E + */ +bool mmu=5Fmap=5Finspect=5Fva(struct pmap *, mmu=5Fmap=5Ft, vm=5Foffset=5F= t); +/*=20 + * Unconditionally allocate resources to setup and "inspect" (as + * above) a given va->pa mapping=20 + */ +void mmu=5Fmap=5Fhold=5Fva(struct pmap *, mmu=5Fmap=5Ft, vm=5Foffset=5Ft= ); + +/* Optionally release resources after tear down of a va->pa mapping */ +void mmu=5Fmap=5Frelease=5Fva(struct pmap *, mmu=5Fmap=5Ft, vm=5Foffset=5F= t); + +/*=20 + * Machine dependant "view" into the page table hierarchy FSM=2E + * On amd64, there are four tables that are consulted for a va->pa + * translation=2E This information may be extracted by the MD functions + * below and is only considered valid between a successful call to + * mmu=5Fmap=5Finspect=5Fva() or mmu=5Fmap=5Fhold=5Fva() and a subsequent= + * call to mmu=5Fmap=5Frelease=5Fva() + */ +pd=5Fentry=5Ft * mmu=5Fmap=5Fpml4t(mmu=5Fmap=5Ft); /* Page Map Level 4 Ta= ble */ +pd=5Fentry=5Ft * mmu=5Fmap=5Fpdpt(mmu=5Fmap=5Ft); /* Page Directory Poin= ter Table */ +pd=5Fentry=5Ft * mmu=5Fmap=5Fpdt(mmu=5Fmap=5Ft); /* Page Directory Tabl= e */ +pd=5Fentry=5Ft * mmu=5Fmap=5Fpt(mmu=5Fmap=5Ft); /* Page Table */ + +#endif /* !=5FXEN=5FMMU=5FMAP=5FH=5F */ Modified: projects/amd64=5Fxen=5Fpv/sys/conf/files=2Eamd64 =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D =3D=3D --- projects/amd64=5Fxen=5Fpv/sys/conf/files=2Eamd64=09Thu May 24 11:52:57= 2012=09(r235903) +++ projects/amd64=5Fxen=5Fpv/sys/conf/files=2Eamd64=09Thu May 24 12:02:10= 2012=09(r235904) @@ -128,6 +128,7 @@ amd64/amd64/mpboot=2ES=09=09optional=09native sm amd64/xen/mpboot=2Ec=09=09optional=09xen smp amd64/amd64/pmap=2Ec=09=09optional=09native amd64/xen/pmap=2Ec=09=09optional=09xen +amd64/xen/mmu=5Fmap=2Ec=09=09optional=09xen amd64/amd64/prof=5Fmachdep=2Ec=09optional=09profiling-routine amd64/amd64/ptrace=5Fmachdep=2Ec=09standard amd64/amd64/sigtramp=2ES=09=09standard -------------------------------------------------------------------- mail2web LIVE =96 Free email based on Microsoft=AE Exchange technology - http://link=2Email2web=2Ecom/LIVE
Want to link to this message? Use this URL: <https://mail-archive.FreeBSD.org/cgi/mid.cgi?380-2201254241730954>