Date: Wed, 7 Jun 1995 13:42:06 +0200 From: esser@zpr.uni-koeln.de (Stefan Esser) To: "Danny J. Zerkel" <dzerkel@feephi.phofarm.com> Cc: freebsd-hackers@freebsd.org Subject: Re: 2.0.5 ALPHA Message-ID: <199506071142.AA07892@FileServ1.MI.Uni-Koeln.DE> In-Reply-To: "Danny J. Zerkel" <dzerkel@feephi.phofarm.com> "Re: 2.0.5 ALPHA" (Jun 6, 21:36)
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On Jun 6, 21:36, "Danny J. Zerkel" wrote:
} Subject: Re: 2.0.5 ALPHA
Since the PCI chip set messages are my code,
I'll comment on some of your questions.
} Here's what dmesg says, by the way:
} CPU: 78-MHz Pentium 735\\90 or 815\\100 (Pentium-class CPU)
} Origin = "GenuineIntel" Id = 0x524 Stepping=4
} Features=0x1bf<FPU,VME,PSE,MCE,CX8,APIC>
} real memory = 16384000 (4000 pages)
} avail memory = 15085568 (3683 pages)
} bt0: Bt946C/ 0-PCI/EISA/VLB(32bit) bus
} bt0: reading board settings, busmastering, int=15
} bt0: version 4.24, sync, parity, 32 mbxs, 32 ccbs
} bt0: targ 0 sync rate=10.00MB/s(100ns), offset=15
} bt0: targ 3 sync rate= 5.00MB/s(200ns), offset=08
} bt0: targ 6 sync rate= 4.54MB/s(220ns), offset=15
Hmm, that's unrelated, but quite interesting ...
The BusLogic seems to negotiate synch. transfers
before knowing the device characteristics (at least
before the SCSI code has issued an INQUIRY command).
} bt0: Enabling Round robin scheme
} bt0 at 0x330 irq 15 on isa
} (bt0:0:0): "CONNER CFP1060S 1.05GB 2035" type 0 fixed SCSI 2
} sd0(bt0:0:0): Direct-Access 1013MB (2074880 512 byte sectors)
} sd0(bt0:0:0): with 2756 cyls, 8 heads, and an average 94 sectors/track
} (bt0:3:0): "HP HP35470A 1109" type 1 removable SCSI 2
} st0(bt0:3:0): Sequential-Access density code 0x13, variable blocks, write-enabled
} (bt0:6:0): "PLEXTOR CD-ROM PX-4XCS 1.01" type 5 removable SCSI 2
} cd0(bt0:6:0): CD-ROM
} cd0(bt0:6:0): NOT READY asc:3a,0 Medium not present
} can't get the size
...
} Probing for devices on the pci0 bus:
} configuration mode 2 allows 16 devices.
} chip0 <Intel 82434LX PCI cache memory controller> rev 17 on pci0:0
} CPU: Pentium, 100MHz, CPU->Memory posting ON
^^^^^^
This 100MHz value is derived from a clock
divider setting in the chip set.
(Don't know where the 78MHz in the first
lines of the boot log come from.)
} Cache: None3-2-2-2/4-2-2-2
^^^^^^^^^^^^^^^^^^^
Hmm, didn't expect that to happen ...
Will fix it when the code freeze is over.
} DRAM: page mode memory clocks=X-4-4-4 (70ns)
The RAM is accessed every 4 clocks, after the
initial lead in cycles. This should suffice
for 70ns DRAMs. If you got 60ns DRAMs, then
you might try to select a X-4-4-4/X-3-3-3
mode, according to the i82434LX data book.
This should be a BIOS option.
} CPU->PCI: posting ON, burst mode ON, PCI clocks=2-1-1-1
} PCI->Memory: posting ON
} chip1 <Intel 82378IB PCI-ISA bridge> rev 3 on pci0:2
} [40] 40420 [50] 0 [54] 4000000
} pci0:3: vendor=0x1095, device=0x640, class=storage [not supported]
} pci0:13: vendor=0x104b, device=0x1040, class=storage [not supported]
} map(10): io(fcfc)
If you know what kind of devices these are,
they can be appended to our PCI vendor and
card list.
} Note: The first line says 78MHz, sometimes it say 100MHz.
} The DRAM: line says "(70ns)", althought I have 60ns memory.
} Is there a way of changing this.
The PCI code only displays values, since we
found that we generally can rely on the BIOS
for initialisation.
If you got 60ns DRAMs, then try to choose a
faster DRAM access mode.
I'm new on the "hackers" list, and missed
most of this thread. Do I understand right,
that you have secondary cache, but had to
disable it to make your system work ?
Regards, STefan
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